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Hari L 2e3e690023 soc/qualcomm/x1p42100: Support to load ADSP Lite firmware
ADSP Lite firmware along with its corresponding DTB must be loaded from coreboot to allow the LPASS/ADSP subsystem to initialize correctly.ADSP lite firmware supports off-mode charging.

This patch adds support to load the ADSP DTB and ADSP firmware images
on the X1P42100 platform. The register programming details required
for loading ADSP are derived from the HRD-X1P42100-S1 document.

Reference:
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
     2. Verified using ADSP load log from coreboot showing successful
        loading of ADSP DTB and ADSP firmware:
        'SOC:LPASS/ADSP image loaded successfully'

Logs:

[INFO ]  Initializing devices...
[DEBUG]  Root Device init
[DEBUG]  Starting cbfs_boot_device
[DEBUG]  FMAP: area FW_MAIN_A found @ c30000 (8904448 bytes)
[INFO ]  CBFS: Found 'fallback/adsp_dtbs' @0x237200 size 0x10794 in mcache @0x8669d794
[DEBUG]  Starting cbfs_boot_device
[INFO ]  CBFS: Found 'fallback/adsp_dtbs' @0x237200 size 0x10794 in mcache @0x8669d794
[DEBUG]  read SPI 0xe67258 0x10794: 3662 us, 18425 KB/s, 147.400 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 67476 bytes, hash algo 2, HW acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f800000
[DEBUG]    code (compression=0)
[DEBUG]    New segment dstaddr 0x866c0000 memsize 0x1075c srcaddr 0x9f800038 filesize 0x1075c
[DEBUG]  Loading Segment: addr: 0x866c0000 memsz: 0x000000000001075c filesz: 0x000000000001075c
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x866c0000, 866d075c, 0x866d075c) <- 9f800038
[DEBUG]  Loading segment from ROM address 0x9f80001c
[DEBUG]    Entry Point 0x866c0000
[SPEW ]  Loaded segments
[DEBUG]  Starting cbfs_boot_device
[INFO ]  CBFS: Found 'fallback/adsp_lite' @0xe7ac0 size 0x14f6aa in mcache @0x8669d73c
[DEBUG]  read SPI 0xd17b18 0x14f6aa: 74126 us, 18534 KB/s, 148.272 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 1373866 bytes, hash algo 2, HW acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f800000
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86b00000 memsize 0x5000 srcaddr 0x9f800268 filesize 0x2072
[DEBUG]  Loading Segment: addr: 0x86b00000 memsz: 0x0000000000005000 filesz: 0x0000000000002072
[DEBUG]  using LZMA
[SPEW ]  [ 0x86b00000, 86b04620, 0x86b05000) <- 9f800268
[DEBUG]  Clearing Segment: addr: 0x0000000086b04620 memsz: 0x00000000000009e0
[DEBUG]  Loading segment from ROM address 0x9f80001c
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x86b05000 memsize 0x240000 srcaddr 0x9f8022da filesize 0x6cf
[DEBUG]  Loading Segment: addr: 0x86b05000 memsz: 0x0000000000240000 filesz: 0x00000000000006cf
[DEBUG]  using LZMA
[SPEW ]  [ 0x86b05000, 86b14ffc, 0x86d45000) <- 9f8022da
[DEBUG]  Clearing Segment: addr: 0x0000000086b14ffc memsz: 0x0000000000230004
[DEBUG]  Loading segment from ROM address 0x9f800038
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d45000 memsize 0x12000 srcaddr 0x9f8029a9 filesize 0xa2d6
[DEBUG]  Loading Segment: addr: 0x86d45000 memsz: 0x0000000000012000 filesz: 0x000000000000a2d6
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d45000, 86d567dc, 0x86d57000) <- 9f8029a9
[DEBUG]  Clearing Segment: addr: 0x0000000086d567dc memsz: 0x0000000000000824
[DEBUG]  Loading segment from ROM address 0x9f800054
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d57000 memsize 0x7000 srcaddr 0x9f80cc7f filesize 0x3c6c
[DEBUG]  Loading Segment: addr: 0x86d57000 memsz: 0x0000000000007000 filesz: 0x0000000000003c6c
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d57000, 86d5da34, 0x86d5e000) <- 9f80cc7f
[DEBUG]  Clearing Segment: addr: 0x0000000086d5da34 memsz: 0x00000000000005cc
[DEBUG]  Loading segment from ROM address 0x9f800070
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d5e000 memsize 0x8000 srcaddr 0x9f8108eb filesize 0x538
[DEBUG]  Loading Segment: addr: 0x86d5e000 memsz: 0x0000000000008000 filesz: 0x0000000000000538
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d5e000, 86d65850, 0x86d66000) <- 9f8108eb
[DEBUG]  Clearing Segment: addr: 0x0000000086d65850 memsz: 0x00000000000007b0
[DEBUG]  Loading segment from ROM address 0x9f80008c
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d70000 memsize 0x1000 srcaddr 0x9f810e23 filesize 0xc4
[DEBUG]  Loading Segment: addr: 0x86d70000 memsz: 0x0000000000001000 filesz: 0x00000000000000c4
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d70000, 86d700f0, 0x86d71000) <- 9f810e23
[DEBUG]  Clearing Segment: addr: 0x0000000086d700f0 memsz: 0x0000000000000f10
[DEBUG]  Loading segment from ROM address 0x9f8000a8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x86d71000 memsize 0x3000 srcaddr 0x9f810ee7 filesize 0x4b1
[DEBUG]  Loading Segment: addr: 0x86d71000 memsz: 0x0000000000003000 filesz: 0x00000000000004b1
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d71000, 86d7384c, 0x86d74000) <- 9f810ee7
[DEBUG]  Clearing Segment: addr: 0x0000000086d7384c memsz: 0x00000000000007b4
[DEBUG]  Loading segment from ROM address 0x9f8000c4
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x86d74000 memsize 0x192000 srcaddr 0x9f811398 filesize 0xafc41
[DEBUG]  Loading Segment: addr: 0x86d74000 memsz: 0x0000000000192000 filesz: 0x00000000000afc41
[DEBUG]  using LZMA
[SPEW ]  [ 0x86d74000, 86f054a4, 0x86f06000) <- 9f811398
[DEBUG]  Clearing Segment: addr: 0x0000000086f054a4 memsz: 0x0000000000000b5c
[DEBUG]  Loading segment from ROM address 0x9f8000e0
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x86f06000 memsize 0x375000 srcaddr 0x9f8c0fd9 filesize 0xb722
[DEBUG]  Loading Segment: addr: 0x86f06000 memsz: 0x0000000000375000 filesz: 0x000000000000b722
[DEBUG]  using LZMA
[SPEW ]  [ 0x86f06000, 86f7392c, 0x8727b000) <- 9f8c0fd9
[DEBUG]  Clearing Segment: addr: 0x0000000086f7392c memsz: 0x00000000003076d4
[DEBUG]  Loading segment from ROM address 0x9f8000fc
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x8727b000 memsize 0x1000 srcaddr 0x9f8cc6fb filesize 0x1d
[DEBUG]  Loading Segment: addr: 0x8727b000 memsz: 0x0000000000001000 filesz: 0x000000000000001d
[DEBUG]  using LZMA
[SPEW ]  [ 0x8727b000, 8727b2a0, 0x8727c000) <- 9f8cc6fb
[DEBUG]  Clearing Segment: addr: 0x000000008727b2a0 memsz: 0x0000000000000d60
[DEBUG]  Loading segment from ROM address 0x9f800118
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x8727c000 memsize 0x15000 srcaddr 0x9f8cc718 filesize 0x3d04
[DEBUG]  Loading Segment: addr: 0x8727c000 memsz: 0x0000000000015000 filesz: 0x0000000000003d04
[DEBUG]  using LZMA
[SPEW ]  [ 0x8727c000, 8729023c, 0x87291000) <- 9f8cc718
[DEBUG]  Clearing Segment: addr: 0x000000008729023c memsz: 0x0000000000000dc4
[DEBUG]  Loading segment from ROM address 0x9f800134
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x87291000 memsize 0x1000 srcaddr 0x9f8d041c filesize 0x16c
[DEBUG]  Loading Segment: addr: 0x87291000 memsz: 0x0000000000001000 filesz: 0x000000000000016c
[DEBUG]  using LZMA
[SPEW ]  [ 0x87291000, 87291587, 0x87292000) <- 9f8d041c
[DEBUG]  Clearing Segment: addr: 0x0000000087291587 memsz: 0x0000000000000a79
[DEBUG]  Loading segment from ROM address 0x9f800150
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x87292000 memsize 0x24600 srcaddr 0x9f8d0588 filesize 0x52c
[DEBUG]  Loading Segment: addr: 0x87292000 memsz: 0x0000000000024600 filesz: 0x000000000000052c
[DEBUG]  using LZMA
[SPEW ]  [ 0x87292000, 872b6600, 0x872b6600) <- 9f8d0588
[DEBUG]  Loading segment from ROM address 0x9f80016c
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x872b6600 memsize 0x2a00 srcaddr 0x9f8d0ab4 filesize 0xef0
[DEBUG]  Loading Segment: addr: 0x872b6600 memsz: 0x0000000000002a00 filesz: 0x0000000000000ef0
[DEBUG]  using LZMA
[SPEW ]  [ 0x872b6600, 872b8de9, 0x872b9000) <- 9f8d0ab4
[DEBUG]  Clearing Segment: addr: 0x00000000872b8de9 memsz: 0x0000000000000217
[DEBUG]  Loading segment from ROM address 0x9f800188
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x872b9000 memsize 0x6c srcaddr 0x9f8d19a4 filesize 0x4b
[DEBUG]  Loading Segment: addr: 0x872b9000 memsz: 0x000000000000006c filesz: 0x000000000000004b
[DEBUG]  using LZMA
[SPEW ]  [ 0x872b9000, 872b906c, 0x872b906c) <- 9f8d19a4
[DEBUG]  Loading segment from ROM address 0x9f8001a4
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x872b906c memsize 0x1cf94 srcaddr 0x9f8d19ef filesize 0xffcc
[DEBUG]  Loading Segment: addr: 0x872b906c memsz: 0x000000000001cf94 filesz: 0x000000000000ffcc
[DEBUG]  using LZMA
[SPEW ]  [ 0x872b906c, 872d5368, 0x872d6000) <- 9f8d19ef
[DEBUG]  Clearing Segment: addr: 0x00000000872d5368 memsz: 0x0000000000000c98
[DEBUG]  Loading segment from ROM address 0x9f8001c0
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x872e0000 memsize 0x1e0000 srcaddr 0x9f8e19bb filesize 0x62e09
[DEBUG]  Loading Segment: addr: 0x872e0000 memsz: 0x00000000001e0000 filesz: 0x0000000000062e09
[DEBUG]  using LZMA
[SPEW ]  [ 0x872e0000, 874bf3c4, 0x874c0000) <- 9f8e19bb
[DEBUG]  Clearing Segment: addr: 0x00000000874bf3c4 memsz: 0x0000000000000c3c
[DEBUG]  Loading segment from ROM address 0x9f8001dc
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x874c0000 memsize 0xef000 srcaddr 0x9f9447c4 filesize 0xd8f
[DEBUG]  Loading Segment: addr: 0x874c0000 memsz: 0x00000000000ef000 filesz: 0x0000000000000d8f
[DEBUG]  using LZMA
[SPEW ]  [ 0x874c0000, 874c4130, 0x875af000) <- 9f9447c4
[DEBUG]  Clearing Segment: addr: 0x00000000874c4130 memsz: 0x00000000000eaed0
[DEBUG]  Loading segment from ROM address 0x9f8001f8
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x875af000 memsize 0x1000 srcaddr 0x9f945553 filesize 0x3a
[DEBUG]  Loading Segment: addr: 0x875af000 memsz: 0x0000000000001000 filesz: 0x000000000000003a
[DEBUG]  using LZMA
[SPEW ]  [ 0x875af000, 875af078, 0x875b0000) <- 9f945553
[DEBUG]  Clearing Segment: addr: 0x00000000875af078 memsz: 0x0000000000000f88
[DEBUG]  Loading segment from ROM address 0x9f800214
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x875b0000 memsize 0x4f000 srcaddr 0x9f94558d filesize 0xa11d
[DEBUG]  Loading Segment: addr: 0x875b0000 memsz: 0x000000000004f000 filesz: 0x000000000000a11d
[DEBUG]  using LZMA
[SPEW ]  [ 0x875b0000, 875fefd4, 0x875ff000) <- 9f94558d
[DEBUG]  Clearing Segment: addr: 0x00000000875fefd4 memsz: 0x000000000000002c
[DEBUG]  Loading segment from ROM address 0x9f800230
[DEBUG]    BSS 0x875ff000 (1052672 byte)
[DEBUG]  Loading Segment: addr: 0x875ff000 memsz: 0x0000000000101000 filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x875ff000, 875ff000, 0x87700000) <- 9f94f6aa
[DEBUG]  Clearing Segment: addr: 0x00000000875ff000 memsz: 0x0000000000101000
[DEBUG]  Loading segment from ROM address 0x9f80024c
[DEBUG]    Entry Point 0x86b00000
[SPEW ]  Loaded segments
[INFO] SOC: LPASS/ADSP image loaded successfully

Change-Id: I04ebd71bc06c971a39f0d4ae9fe299a64dfaaff8
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2026-03-25 00:36:08 +00:00
3rdparty 3rdparty/intel-microcode: Update to upstream main 2026-03-19 16:30:20 +00:00
configs configs: Remove starbook/adl option table config 2026-03-05 17:50:00 +00:00
Documentation Documentation: Finalize 26.03 release notes 2026-03-21 18:25:10 +00:00
LICENSES LICENSES: Add LGPL 2.1 license 2024-02-18 01:56:38 +00:00
payloads {commonlib, libpayload}: Add RTC_WAKE to boot_mode_t 2026-03-21 03:04:17 +00:00
spd spd/lp5x: Generate initial SPD for SL5D32G32C2A-HC0 2026-03-24 14:47:02 +00:00
src soc/qualcomm/x1p42100: Support to load ADSP Lite firmware 2026-03-25 00:36:08 +00:00
tests commonlib/device_tree: Utilize list_move() in dt_copy_subtree() 2026-03-07 01:19:35 +00:00
util amdfwtool: Allow to set bios entry 0x6d (AMD_BIOS_NV_ST) 2026-03-21 18:25:52 +00:00
.checkpatch.conf .checkpatch.conf: Set max line length to 96 2024-12-04 07:36:22 +00:00
.clang-format Treewide: Fix incorrect SPDX license strings 2024-02-18 01:55:57 +00:00
.editorconfig .editorconfig: Add indent style & size of 2 spaces for shell 2023-12-20 22:30:33 +00:00
.gitignore .gitignore: Add .clangd as a "Development friendly file" 2025-10-24 21:35:19 +00:00
.gitmodules vc/amd/opensil: Add Phoenix OpenSIL POC directory as a copy of Genoa 2026-03-13 16:43:33 +00:00
.gitreview .gitreview: Update default branch from master to main 2023-12-23 16:44:31 +00:00
.mailmap .mailmap: Add a .mailmap file for git 2022-03-08 18:53:47 +00:00
AUTHORS AUTHORS: Update list to 25.03 2025-05-08 22:32:29 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
gnat.adc drivers/intel/gma: Allow SPARK function with side effects 2024-03-01 18:46:30 +00:00
MAINTAINERS MAINTAINERS: Add Nicholas Chin for autoport 2026-03-04 14:19:07 +00:00
Makefile Reland "tests: Allow specifying vboot source directory" 2025-09-16 15:04:07 +00:00
Makefile.mk Makefile.mk: generate EDK2 update capsule 2026-03-16 19:51:14 +00:00
README.md Documentation: Update internal URL's 2024-01-04 14:22:51 +00:00
toolchain.mk tree: Replace scan-build by clang-tidy 2025-07-01 01:12:32 +00:00

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary firmware (BIOS/UEFI) found in most computers. coreboot performs the required hardware initialization to configure the system, then passes control to a different executable, referred to in coreboot as the payload. Most often, the primary function of the payload is to boot the operating system (OS).

With the separation of hardware initialization and later boot logic, coreboot is perfect for a wide variety of situations. It can be used for specialized applications that run directly in the firmware, running operating systems from flash, loading custom bootloaders, or implementing firmware standards, like PC BIOS services or UEFI. This flexibility allows coreboot systems to include only the features necessary in the target application, reducing the amount of code and flash space required.

Source code

All source code for coreboot is stored in git. It is downloaded with the command:

git clone https://review.coreboot.org/coreboot.git.

Code reviews are done in the project's Gerrit instance.

The code may be browsed via coreboot's Gitiles instance.

The coreboot project also maintains a mirror of the project on github. This is read-only, as coreboot does not accept github pull requests, but allows browsing and downloading the coreboot source.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://doc.coreboot.org/payloads.html for a list of some of coreboot's supported payloads.

Supported Hardware

The coreboot project supports a wide range of architectures, chipsets, devices, and mainboards. While not all of these are documented, you can find some information in the Architecture-specific documentation or the SOC-specific documentation.

For details about the specific mainboard devices that coreboot supports, please consult the Mainboard-specific documentation or the Board Status pages.

Releases

Releases are currently done by coreboot every quarter. The release archives contain the entire coreboot codebase from the time of the release, along with any external submodules. The submodules containing binaries are separated from the general release archives. All of the packages required to build the coreboot toolchains are also kept at coreboot.org in case the websites change, or those specific packages become unavailable in the future.

All releases are available on the coreboot download page.

Please note that the coreboot releases are best considered as snapshots of the codebase, and do not currently guarantee any sort of extra stability.

Build Requirements and building coreboot

The coreboot build, associated utilities and payloads require many additional tools and packages to build. The actual coreboot binary is typically built using a coreboot-controlled toolchain to provide reproducibility across various platforms. It is also possible, though not recommended, to make it directly with your system toolchain. Operating systems and distributions come with an unknown variety of system tools and utilities installed. Because of this, it isn't reasonable to list all the required packages to do a build, but the documentation lists the requirements for a few different Linux distributions.

To see the list of tools and libraries, along with a list of instructions to get started building coreboot, go to the Starting from scratch tutorial page.

That same page goes through how to use QEMU to boot the build and see the output.

Website and Mailing List

Further details on the project, as well as links to documentation and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://doc.coreboot.org/community/forums.html

Copyrights and Licenses

Uncopyrightable files

There are many files in the coreboot tree that we feel are not copyrightable due to a lack of creative content.

"In order to qualify for copyright protection in the United States, a work must satisfy the originality requirement, which has two parts. The work must have “at least a modicum” of creativity, and it must be the independent creation of its author."

https://guides.lib.umich.edu/copyrightbasics/copyrightability

Similar terms apply to other locations.

These uncopyrightable files include:

  • Empty files or files with only a comment explaining their existence. These may be required to exist as part of the build process but are not needed for the particular project.
  • Configuration files either in binary or text form. Examples would be files such as .vbt files describing graphics configuration, .apcb files containing configuration parameters for AMD firmware binaries, and spd files as binary .spd or text *spd*.hex representing memory chip configuration.
  • Machine-generated files containing version numbers, dates, hash values or other "non-creative" content.

As non-creative content, these files are in the public domain by default. As such, the coreboot project excludes them from the project's general license even though they may be included in a final binary.

If there are questions or concerns about this policy, please get in touch with the coreboot project via the mailing list.

Copyrights

The copyright on coreboot is owned by quite a large number of individual developers and companies. A list of companies and individuals with known copyright claims is present at the top level of the coreboot source tree in the 'AUTHORS' file. Please check the git history of each of the source files for details.

Licenses

Because of the way coreboot began, using a significant amount of source code from the Linux kernel, it's licensed the same way as the Linux Kernel, with GNU General Public License (GPL) Version 2. Individual files are licensed under various licenses, though all are compatible with GPLv2. The resulting coreboot image is licensed under the GPL, version 2. All source files should have an SPDX license identifier at the top for clarification.

Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms. As an exception, files under Documentation/ with a history older than 2017-05-24 might be under different licenses.

Files in the coreboot/src/commonlib/bsd directory are all licensed with the BSD-3-clause license. Many are also dual-licensed GPL-2.0-only or GPL-2.0-or-later. These files are intended to be shared with libpayload or other BSD licensed projects.

The libpayload project contained in coreboot/payloads/libpayload may be licensed as BSD or GPL, depending on the code pulled in during the build process. All GPL source code should be excluded unless the Kconfig option to include it is set.

The Software Freedom Conservancy

Since 2017, coreboot has been a member of The Software Freedom Conservancy, a nonprofit organization devoted to ethical technology and driving initiatives to make technology more inclusive. The conservancy acts as coreboot's fiscal sponsor and legal advisor.