Add DSI power-off commands for TM_TL121BVMS07_00C, so that payloads can
run it to properly disable the display.
Also refactor the init commands using MIPI_DCS_* macros to improve
readability.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I0e7da1d23c658d7f3594cbb651c229057810319c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90740
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add verification to ensure that the integrated GPU is available,
avoiding crashes in FSP-M and FSP-S. The problem was first identified
on Skylake systems where the iGPU is missing or disabled, particularly
when VT-D is enabled, which can cause FSP-S to hang during boot.
Enabling SGX hides the issue, but it also leads to unstable
virtualization.
Apply the fix to Alderlake, Cannonlake, and Tigerlake SoCs in addition
to Skylake.
TEST=Build and boot to OS (Windows, Proxmox). Check to verify
functions work. (Skylake H110 + Xeon E3-1245 V5, E3-1260L V5,
i7-6700K, i3-7100)
Change-Id: I394f46ed5a277218a8dd587705eaecabe59fd110
Signed-off-by: Ulysse Ballesteros <ulysseballesteros@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89821
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
List of changes:
- Increase the delay between romstage and ramstage GPIO init sequence.
- Delay the USB host initialization to meet the timing requirements.
BUG=b:475214332
TEST=Verify USB 3.0 storage key detection on Google/Quartz.
Change-Id: Ib6044b1e65fe0fe2fde5b688a9491d6e3fc75727
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90758
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On mc_ehl6/7 mainboards, the internal GPIO pull-up is required for the
SD card "Card Detect" signal to function properly.
This patch updates the GPIO configuration accordingly.
TEST=Booted mc_ehl6 and verified the voltage level at the
relevant pin before and after the patch.
Change-Id: I96a381f100dd9886ced030434316125d60a13a72
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90769
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this board, different I2C controllers must be activated and a
different RTC chip is used compared to mc_ehl1.
TEST=Booted into OS and verified that all relevant devices are detected.
Change-Id: If2990b7d8d599c6e5f5841d8018d2a3f00dbc515
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90766
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the PCIe root port settings, as the PCIe topology
differs from the mc_ehl1 mainboard.
TEST=Booted into OS and verifed that all relevant PCIe devices are
detected.
Change-Id: I0953a139b63080489128cc0a0dc865b65632b575
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90765
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard is based on mc_ehl1. As a first step, it contains a copy
of the mc_ehl1 directory with minimal changes.
Special adaptations for mc_ehl8 mainboard will follow in separate
commits.
TEST=Built siemens/mc_ehl8 successfully.
Change-Id: Icf8e90e7d3ed58ea4500cb6132fef37e32c5a4c2
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90764
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On AMD platforms the PSP can boot from different SPI CS lines
and do a recovery boot in case the default CS0 isn't usable.
Allow the SoC to provide the current boot_device CS line by
adding a new weak function.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9ed54b7979405d433f22458265f09701cda842e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For all functions which check flags, return a bool type instead of an
int type.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I39f0e2f392ec999f7622ed28c5755dd4d0eecf42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This CL update max TDP from 6W to 7W as requested by thermal team.
Increase tdp_pl1_override value from 6 W to 7 W.
Increase PL1 max power value from 6 W to 7 W.
The settings has been verified by thermal team.
BUG=b:476292154, b:476292156
TEST=emerge-nissa coreboot chromeos-bootimage
verified test result by thermal team
Change-Id: Iaedfb2caec589dd5f5be5cc872e302d55fa51dd6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Replace backup file mechanism with git restore to fix restoration
bugs and simplify the build system. Files are now always restored
after build completion, ensuring a clean git state regardless of
which configuration options modify the config files.
TEST=build samsung/stumpy with iPXE for edk2 twice in a row without
failure due to dirty repo state.
Change-Id: I9c88f5ca5e5a0172f7c0a94e4edfe0192340d1e2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90772
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent changes to iPXE related to UEFI SecureBoot handling are causing
builds to break, so update the "stable" tag to the last commit in
December 2025 and use that by default until things are sorted out in
the master branch.
TEST=build samsung/stumpy with iPXE for edk2
Change-Id: I5ccdbbf35273cf1e963b913327ffa94df46a1497
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90771
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit e59c5abd13 ("ec/google/chromeec: Add
EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC") refactored cbi_get_uint32() to
write directly to the caller's buffer instead of using a local variable.
This caused uninitialized memory (containing garbage addresses) to be
passed to the EC as the return buffer during CBI reads.
In the case of google/zork, the call to
google_chromeec_cbi_get_board_version() returned garbage data (e.g.,
0xae6ccd05 vs 0x5) which caused incorrect code paths to be taken:
- variant_override_gpio_table() selected wrong GPIO tables based on
invalid board version comparisons
- variant_touchscreen_update() skipped touchscreen GPIO configuration
because variant_uses_v3_6_schematics() returned true for garbage
values
- variant_uses_codec_gpi() returned wrong value, preventing
headphone jack interrupt setup
These misconfigurations caused input devices (touchpad, touchscreen,
trackpoint) to be non-functional, despite being detected by the OS.
The fix restores the original behavior by using a local variable
initialized to 0, ensuring a clean buffer is always passed to the EC.
TEST=build/boot google/zork, verify board version is read correctly,
all input devices functional under Linux/Windows.
Change-Id: Ia7be0bcc588075ab5c994edc3d68e979cc01ac79
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the lb_panel_poweroff/cb_panel_poweroff structs to pass the
panel power-off commands from coreboot to payloads.
Also add mipi_panel_parse_commands() to libpayload libc, so that
payloads can utilize it to parse the power-off commands.
BUG=b:474187570
TEST=emerge-jedi coreboot libpayload
BRANCH=skywalker
Change-Id: I652178c8075a1f3aee356502e682ef9a4f3d1cf8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the trace length for the card reader USB port, and based on this
value adjust the macro used accordingly.
Change-Id: I1c7661f492b9193b75ed39abb2f5d14614cfc213
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90675
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `card_reader` option is only available on specific boards,
so to avoid enabling a USB port that isn't connected, set the
fallback value to 0 instead of 1.
Change-Id: Ied540d6242758663db7a7a11fbefb5c4a84b942d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90770
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support for the Ibex Peak chipset was added in commit 888d559b03
("Support for Ibexpeak southbridge") by copy-pasting the bd82x6x
implementation and making appropriate changes. This resulted in some
of the PCI IDs for 6/7 series chipsets being left behind.
While some of these PCI IDs were removed in a commit b7d8788880
("ibexpeak/lpc: Fix PCIIDs."), there are still some that remain, we
remove those in this commit.
Change-Id: I5dc0e4fb2694eec9ef6246e0ae9211dff604d5b9
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89569
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Using generics (introduced in go 1.18) we can avoid repeating the same
code multiple times by encapsulating it into a generic function.
Change-Id: I5dc6696f8802d3fe57290121e22b2c27c545d3ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas <nic.c3.14@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously, `KconfigBool` was used to generate selects (if the option
value is true) or bool option overrides (if the option value is false).
This approach is not particularly flexible: one cannot have conditions
for selects, and bool option overrides can only disable options.
Introduce a new `KconfigStatement` map of Kconfig names to conditions.
An empty condition string means that no condition is to be added. Also
update uses of `KconfigBool` to `KconfigSelect` to preserve autoport's
current behaviour.
TEST=Generated files for HP ProBook 4740s (Sandy Bridge) do not change.
Change-Id: I88666ce0d761c1d393ac602196229ec0878fed42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This update introduces support for Google touchscreen devices
to the existing framework, enhancing compatibility with Google's
hardware interfaces. It extends the fw_config field with new
options to accommodate different connection types used by Google
touchscreens. Specifically, it adds:
- TOUCHSCREEN_LPSS_I2C_ELAN_REX for ELAN9006 interfaced via LPSS-I2C.
- TOUCHSCREEN_THC_SPI_ELAN_REX for ELAN6918 interfaced via THC-SPI.
- TOUCHSCREEN_THC_I2C_ELAN_REX for ELAN9006 interfaced via THC-I2C.
BUG=none
TEST=Connect Google's REX touchscreen with the conversion cables. Boot
to OS with fw_config setting for Google's touchscreen and verify
device enumeration in /sys/bus/hid/devices directory.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3fda0e4587d8484881c844674053a0badfc23a11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89181
Reviewed-by: Kim, Kyoung Il <kyoung.il.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard no SATA interface is assembled. Therefore, it is
deactivated.
TEST=Boot into OS and verify via lspci if relevant SATA Controller is
deactivated and no error in coreboot log is shown.
Change-Id: Iea01c30d18d81e67087ac8abef5cece0040087e5
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90730
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the unused GbE and PSE TSN GbE device 0. These devices are not
required for the current board functionality. Removing them simplifies
the configuration.
Also PSE is not used for any other functionality, the local host
interface is deacitivated as well.
TEST=Check if all other GbE ports of mainboard still work.
Change-Id: I83c7e9731d3684a0b0a7f16b533ee3ea2989f3c6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90726
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add AX211 wifi sar table for gothrax wifi sar config.
Use fw_config to separate different wifi card settings.
WLAN_AX211_Intel: 1
BUG=b:454207611
Test=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I11cf6cd61a13f5365530fc07b589d749c9459d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
`VBOOT_EARLY_EC_SYNC` enables EC software sync in romstage.
This is useful to achieve full USB-PD negotiation early in the boot
flow. It eliminates a problem where PMC is wrongly configured in
depthcharge during the EC-sync scenario which prevents USB devices
from getting detected when connected via a self-powered USB hub.
`VBOOT_EC_SYNC_ESOL` displays early sign-of-life (eSOL) during EC
firmware updates.
BUG=b:386920751,b:467506959,b:468885646
TEST=Verify detection and booting to OS from USB drive connected to
the Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Verify that eSOL is displayed during EC firmware update.
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I612b4dc13be2efaee863e6cacf8fc4c432edc313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90762
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Relocate the CBMEM top address from a hardcoded 0xC7800000 to the
start of the XBL log region (_dram_xbl_log).
This change moves the CBMEM region from the high Linux Kernel Reserve
block down into the lower DRAM Space 0, adjacent to other firmware
reserved regions. This consolidation prevents marking CBMEM range as
`reserved` and ensures CBMEM is placed in a more stable memory location
(marked available aka System RAM).
- Remove CBMEM_TOP define from addressmap.h.
- Update cbmem_top_chipset() to return (uintptr_t)_dram_xbl_log.
- Update memlayout.ld documentation to reflect the new memory map.
BUG=none
TEST=Boot on X1P42100 platform, verify CBMEM console and tables are
accessible and correctly located via 'cbmem -l'.
w/o this patch:
```
c7800000-cb7fffff : reserved
```
w/ this patch:
```
815a0000-819fffff : System RAM
```
Change-Id: I7392bb7a62d50640696301931940a7baa00351e3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90760
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
I use this to dump SIO config on an HP Z210 CMT workstation.
It's a shotgun blast into the dark, although based on what was
done for Z220, already in tree.
Change-Id: I83184f29c11c92384f6a09b671ed9e24956e9e57
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82627
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("S5VM17" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Ubuntu 25.10) on google/redrix, verify MIPI
camera functional under both OSes using the Intel IPU6 driver stack.
Change-Id: Ic72a96e93706c096b3839ab4c951e1d0a725b5ce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90744
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Update device tree configuration to work with the newly-added Windows/
Linux ACPI device type mode (MIPI_ACPI_TYPE_WINDOWS_LINUX):
- Add IPUA device to GFX generic driver as non-VGA device (required for
IPU enumeration in Windows/Linux mode where IPU is attached to iGPU)
- Add sensor_name ("CJFLE23" and "CJFLE25") for device identification
TEST=build/boot Win11/Linux (Arch) on google/kano, verify MIPI camera
functional under both OSes using the Intel IPU6 driver stack.
Change-Id: I9232318c30ba0eee6dcd54f7199f6995a8ffa48b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90743
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As there is no model of the X280 with a dGPU, its devicetree does not
declare a device with a dgpu alias like the other Skylake/Kaby Lake
Thinkpad ports. This breaks the DEV_PTR(dgpu) reference in cfr.c,
causing the following build error if CONFIG_DRIVERS_OPTION_CFR is set:
In file included from src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:9:
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c: In function 'update_dgpu':
build/static.h:11:33: error: '_dev_dgpu_ptr' undeclared (first use in this function); did you mean '_dev_igpu_ptr'?
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
build/static.h:11:33: note: each undeclared identifier is reported only once for each function it appears in
11 | #define DEV_PTR(_alias) _dev_##_alias##_ptr
| ^~~~~
src/mainboard/lenovo/sklkbl_thinkpad/cfr.c:14:31: note: in expansion of macro 'DEV_PTR'
14 | struct device *dgpu = DEV_PTR(dgpu);
| ^~~~~~~
make: *** [Makefile:431: build/ramstage/mainboard/lenovo/sklkbl_thinkpad/cfr.o] Error 1
Fix this by declaring a WEAK_DEV_PTR for the dgpu device, which will be
overridden by the compiled devicetree if the board variant declares a
dgpu device in its overridetree.
TEST=X280 builds successfully with the following defconfig:
CONFIG_VENDOR_LENOVO=y
CONFIG_BOARD_LENOVO_X280=y
CONFIG_DRIVERS_OPTION_CFR=y
Change-Id: I18cc18a88851bb943de8ab6d2d1fdcbf0f4aea86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90674
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a hooks that will populate mem_info structure with DIMM data
obtained from OpenSIL. As the memory population may be SoC-specific,
call a SoC-specific hook to fill the data.
Change-Id: I0b489c685877ac56f45e0e3abd0bd1b64549585b
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It updates the target variable that is used for `clang -target`.
Simply because the format was wrong. According to the documentation the
format of the so called "target triple" is:
<arch><sub>-<vendor>-<sys>-<env>
with:
arch = x86_64, i386, arm, thumb, mips, etc.
sub = for ex. on ARM: v5, v6m, v7a, v7m, etc.
vendor = pc, apple, nvidia, ibm, etc. (can be omitted)
sys = none, linux, win32, darwin, cuda, etc.
env = eabi, gnu, android, macho, elf, etc.
In case of powerpc that causes an issue when trying to update clang to
version 21. The target parameter for clang ends up being
"powerpc64-none-unknown-linux-gnu". After testing, it turns out that in
clang version 18 that is actually a valid target parameter, although not
according to the documentation. In clang 21 however its not valid so fix
it accordingly.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I958416e6c56459766794830fbeac57ac827ffdd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update the default MrChromebox branch to uefipayload_2511.
This branch is rebased on the latest upstream edk tag
'edk2-stable202511', and includes a number of other improvements,
such as setup menu password protection.
TEST=tested on multiple ChromeOS devices from Sandybridge through
Meteorlake.
Change-Id: I5addbcf37e0b1a1afbd731163b4419d4bd9a3747
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90747
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make EDK2_DEBUG automatically select CONSOLE_SERIAL, require
EDK2_CBMEM_LOGGING to depend on EDK2_RELEASE, and make serial console
mutually exclusive with CBMEM logging. Revise the Kconfig text to
indicate the option is for the serial console, not serial debug output.
This prevents users from selecting options which conflict or will
result in a different result than expected. It simplifes the build
options into 4 clear choices:
- Release build
- Release build with cbmem logging
- Release build with serial console support
- Debug build with serial debugging + serial console support
TEST=build/boot google/drobit with above 4 build configurations.
Change-Id: I15bbbcfcb2d9d0b1d4c2074f2c33012ec94f6c01
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a Kconfg option to allow the SoC to add vendor specific
BERT entries, not yet defined in the ACPI spec. The function
only has to return the size of payload data and the generic
code will allocate space on the BERT table.
The caller must fill in all BERT fields since the generic
code doesn't know anything about the BERT entry.
Change-Id: I361700098ce1a3cc6acae991456a1901d2f07fb6
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90639
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 292d7b9d3d.
The resume failure is caused by the improper DEVAPC setting in fsp_init
for DM/PM and SPM. If fsp_init runs prior to dpm_init and spm_init, it
requires AP to grant the access to DM/PM and SPM from DEVAPC. The fix is
done in CB:90756.
BUG=b:474254985
TEST=Run suspend/resume test
Change-Id: Id21327f6d65d31659cdb8b4bda3b0a0510c438e8
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Modify the Wacom digitizer HID to support the Samsung S-pen. This allows
a different driver to attach under Windows, which adds support for the
side buttons as eraser function and air command.
TEST=build/boot kahaku, verify S-pen works under Windows/Linux
Change-Id: I60b75f7f16f6bb028ad1747e78cc49cac810fc92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90735
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no wifi_mtcl.bin file publicly available, nor can it be
extracted from the stock Google firmware for YAVIKS, so restrict
USE_MTCL to downstream ChromeOS builds since validate_mtcl() fails
when no file is present in CBFS.
TEST=build/boot yaviks, verify no MTCL error in cbmem
Change-Id: I450db6fd8c460109aa4e491d88ec874c5f6429d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90734
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
All cyan-based boards define the size of the BIOS region in their IFD
as 6MB in size; it is likewise defined as such in chromeos.fmd. To
avoid having to override this in the board's config file when building
with a modern payload like edk2, set the default CBFS_SIZE to 6MB as
well to avoid issues with the payload not fitting.
TEST=build/boot google/edgar w/edk2 payload and default CBFS_SIZE
Change-Id: I17122aa2eb9848799c284d13d8c903ad125092b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90733
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CFR support was added in commit c1f0be39da ("mb/google/zork:
Add CFR option menu support"), a comma was inadvertently left off
the end the first CFR object in the list, which breaks compilation.
Fix this by adding the missing comma.
TEST=build/boot zork
Change-Id: I5f13d87cbc81f440b0c14d253a6334adab45631e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90732
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous implementation used the logical OR (||) operator to select
between config->tdp and get_cpu_tdp(). In C, the || operator returns a
boolean value (0 or 1), not the value of the first true operand. This
caused the function to return incorrect TDP values.
This commit replaces the logical OR with the ternary operator (?:),
ensuring that config->tdp is returned if it is non-zero; otherwise,
get_cpu_tdp() is used. This change restores the intended behavior of
selecting the correct TDP value.
TEST=The power map is properly found and applied on a Panther Lake B005
SoC.
Change-Id: I3a02f804510f87cb4d28bd929869570c355c5242
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90759
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add and enable IOST feature to support Intel's IO Self-Testing Software
(IOST), which is an OS tool for performing electrical margining analysis
on USB4 Host and Device Routers, DP2.1 displays, memory, UFS, and PCIe
Gen4+ devices. This change includes the IOST ACPI device in the SoC's
southbridge ASL and implements the SoC-specific soc_fill_p2sb_ssdt
function used by the common P2SB code to generate ACPI code for enabling
IOST in the DSDT. Additionally, the CBFS option "iost_enable" is
required to enable IOST. Command to add this option to the image:
cbfstool <coreboot_image> add-int -r COREBOOT -i 1 -n option/iost_enable
Note that this cbfstool command is an example, for its syntax format
could be changed in the future versions.
BUG=none
TEST=Build coreboot and add the CBFS option flag to the built image.
Boot to OS and verify IOST can access P2SB registers through the ACPI
interface for electrical margining tests.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I6929fa3a44646c5385199a8b1e3d0b681d36c9cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add ACPI device for Intel's IO Self-Testing Software (IOST), which is an
OS tool for performing electrical margining analysis on USB4 Host and
Device Routers, DP2.1 displays, memory, UFS, and PCIe Gen4+ devices.
This ACPI device provides the necessary P2SB access interface to enable
IOST to interact with hardware registers for comprehensive IO testing
and validation. The ASL file should be included in the SoC's
southbridge.asl.
BUG=none
TEST=Build coreboot with this ASL file included in the SoC's
southbridge.asl. Boot to OS and verify IOST objects appear correctly in
the DSDT tables.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I9417da8322931c2afbf75aa9062bceb52b8320d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90128
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add weak function to fill SSDT for SoC-specific P2SB extensions. SoCs
can implement this function to fill additional P2SB-related ACPI
objects. For instance, a SoC might include the IOST ACPI interface that
uses P2SB and enable it via SSDT for debug purposes at the OS level.
BUG=none
TEST=This change cannot be tested in isolation as it only adds an empty
weak function. Testing requires SoCs to implement the function. Add the
necessary code with the same function name in the SoC to generate ACPI
objects and examine the SSDT for changes after boot.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I352f13b9b05dc4b61608a33c76946883bf0d3de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add CPUID definition and CPU table entry for Intel Nova Lake processor
(CPUID 0x300f30). This enables basic CPU initialization and
multiprocessor support for Nova Lake platforms
Reference:
- Nova Lake External Design Specification (EDS) Volume 1 (#844316)
BUG=none
Change-Id: Iea89ebfa8bae3448edfb3b757443ec9902cede5e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Based on the "TCG ACPI Specification" Version 1.3 published 2021.
Add an enum for the ACPI start methods and use it instead of hardcoding
various numbers in plain code.
Change-Id: I8b66527ee7417e231fe52e0a609b8c100de522b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89458
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The AMD fTPM uses the CRB interface, but doesn't implement all registers
defined in the TCG specification. Add a new driver that deals with the
reduced register set.
The reduced CRB MMIO register space has:
- A START register to ring the doorbell
- An error STATUS register with only one bit
- DMA address and size register for the CRB
- No other status or control registers
- No way to read current locality (assumption is locality 0)
- No interface ID register
- No read only registers
The TPM interface also assumes that the DRTM is always using locality 0.
The fTPM needs to access the SPI flash and this is currently done using
the PSP SMI handler. Thus the fTPM will only operate after SMM has been
set up.
The fTPM needs the PSP directory files type 0x04 and type 0x54. When
the regions are missing or corrupted the fTPM won't be operational.
Based off https://github.com/teslamotors/coreboot/tree/tesla-4.12-amd
TEST=Works on AMD glinda (Fam 1Ah).
This adds the following new log messages:
[DEBUG] PSP: Querying PSP capabilities...OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM: CRB buffer created at 0x7b5ee000
[SPEW ] fTPM: CRB TPM initialized successfully
[INFO ] Initialized TPM device fTPM
...
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] TPM2 log created at 0x7b5b1000
[DEBUG] PSP: Querying fTPM capabilities... OK
[DEBUG] ACPI: * TPM2
[DEBUG] ACPI: added table 4/32, length now 68
Change-Id: I780bdab621228e12b37f3a89868e16bc62a05e7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Update the PS1 threshold values for VR_DOMAIN_IA, VR_DOMAIN_GT, and
VR_DOMAIN_SA from 20 A to 15 A, following the recommendations in the
Panther Lake H Platform Design Guide (Draft > 2.1). This change ensures
that power state thresholds are consistent with the most recent platform
specifications, improving accuracy and system behavior under varying
power conditions.
TEST=Fatcat device boots to OS.
Change-Id: I358d4d94c3800ff5b658cb875c90ee7409d86377
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90727
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the board to perform a hardware reboot when the TCO watchdog
expires. This is achieved by using the default Kconfig option
SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN with 'n'.
TEST=Verified in the OS on mc_ehl7:
Checked IO-mapped register 0x408 Bit 0.
Without this patch, the bit is 1 (No Reboot enabled).
With this patch, the bit is 0 (Reboot on expiry enabled).
Change-Id: If3bee9db84c92480762f8a802031d2b01541dbdb
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
