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mb/siemens/mc_ehl8: Configure PCIe root ports

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This patch updates the PCIe root port settings, as the PCIe topology
differs from the mc_ehl1 mainboard.

TEST=Booted into OS and verifed that all relevant PCIe devices are
detected.

Change-Id: I0953a139b63080489128cc0a0dc865b65632b575
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90765
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Uwe Poeche 2025-10-07 08:26:16 +02:00 • committed by Matt DeVillier
commit d810257008
1 changed files with 16 additions and 6 deletions
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22
src/mainboard/siemens/mc_ehl/variants/mc_ehl8/devicetree.cb
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@ -55,19 +55,29 @@ chip soc/intel/elkhartlake
register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
# Disable all L1 substates for PCIe root ports
register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
register "PcieRpL1Substates[6]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports
register "PcieRpLtrDisable[0]" = "true"
register "PcieRpLtrDisable[1]" = "true"
register "PcieRpLtrDisable[2]" = "true"
register "PcieRpLtrDisable[3]" = "true"
register "PcieRpLtrDisable[4]" = "true"
register "PcieRpLtrDisable[5]" = "true"
register "PcieRpLtrDisable[6]" = "true"
# Enable PCIe PTM (Precision Time Measurement) for all PCIe root ports
register "PciePtm[2]" = "true"
register "PciePtm[3]" = "true"
register "PciePtm[4]" = "true"
register "PciePtm[5]" = "true"
register "PciePtm[6]" = "true"
# Determine PCIe root port speed
register "PcieRpPcieSpeed[5]" = "2"
# Storage (SATA/SDCARD/EMMC) related UPDs
register "SataSalpSupport" = "0"
register "SataPortsEnable[0]" = "1"
@ -145,10 +155,10 @@ chip soc/intel/elkhartlake
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # RP1 (pcie0 single VC)
device pci 1c.1 on end # RP2 (pcie0 single VC)
device pci 1c.2 on end # RP3 (pcie0 single VC)
device pci 1c.3 on end # RP4 (pcie0 single VC)
device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1c.5 on end # RP6 (pcie2 multi VC)
device pci 1c.6 on end # RP7 (pcie3 multi VC)
device pci 1e.0 on end # UART0