Maximilian Brune 97291b5838 soc/amd/cezanne: Optionally propagate UART0 through ACPI ... Unable to passthrough the UART0 in domU when UART1 enabled in dom0 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I7ccf366dbac556f68096382644f3e72b13e2dbf9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90210 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-11-27 17:55:20 +00:00
..
acpi	acpigen_ps2_keybd: map insert	2025-11-22 18:55:53 +00:00
arch	memlayout: Introduce PRERAM and POSTRAM DMA coherent regions	2025-11-22 17:23:55 +00:00
commonlib	commonlib: Add CBMEM ID to store boot mode	2025-11-26 18:56:39 +00:00
console	console: Fix flushing for slow consoles	2025-10-02 22:44:46 +00:00
cpu	Makefile.mk: separate bootblocks into BOOTBLOCK and TOPSWAP	2025-11-16 18:35:27 +00:00
device	device: Introduce reworked azalia verb table	2025-09-28 18:18:14 +00:00
drivers	drivers/hwid_dmi: Populate SMBIOS product name from CBFS hwid file	2025-11-23 20:07:54 +00:00
ec	ec/google/chromeec/cfr: Fix CFR callback signatures	2025-11-25 16:50:04 +00:00
include	device/pci_ids: Add DIDs for TGL-H (GT1 and RM590E)	2025-11-26 18:57:46 +00:00
lib	lib/edid_fill_fb: Add dual pipe flag to lb_framebuffer_flags	2025-11-18 07:37:20 +00:00
mainboard	mb/amd/crater: Configure UART1 GPIOs	2025-11-27 17:54:47 +00:00
northbridge	Haswell NRI: Print and fill in memory-related info	2025-10-29 16:52:51 +00:00
sbom	sbom: Fix build with merged bootblock and romstage	2025-07-07 14:29:29 +00:00
security	tree: Use boolean for s3resume	2025-10-23 13:34:15 +00:00
soc	soc/amd/cezanne: Optionally propagate UART0 through ACPI	2025-11-27 17:55:20 +00:00
southbridge	tree: Use boolean for s3resume	2025-10-23 13:34:15 +00:00
superio	sio/nuvoton/common/nuvoton.h: Add common Nuvoton SIO LDNs	2025-10-29 16:56:07 +00:00
vendorcode	src/vc/amd/fsp: fix type 17 DMI info	2025-11-27 17:54:30 +00:00
Kconfig	Kconfig: Introduce HAVE_CBFS_FILE_OPTION_BACKEND	2025-09-17 04:18:07 +00:00