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coreboot/src/soc/intel/cannonlake
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Matt DeVillier fbc2d76ab3 soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as appropriate 
These will be used in subsequent patches which optimize the reading of
SPDs based on the supported memory type(s).

Change-Id: I8b0d4f37b4b992c42bede25d678cb9afc9db3dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88521
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2025-08-02 01:46:21 +00:00
..
acpi soc/intel/cannonlake: Use common ACPI code for SRAM and HECI 2025-03-17 20:20:33 +00:00
bootblock soc/intel/cml, pci_ids: Remove IDs of non-existent graphics devices 2024-09-11 13:40:48 +00:00
include/soc soc/intel: Move CNVI sideband definitions to SoC-specific files 2025-06-16 10:37:49 +00:00
romstage soc/intel/cannonlake: Add/use enums for IGD config 2025-05-14 18:13:20 +00:00
acpi.c soc/intel/cannonlake: Change the maximum C state to C8 2025-01-29 11:45:31 +00:00
chip.c soc/intel/cannonlake: Drop redundant PcieRpEnable 2025-04-23 14:15:39 +00:00
chip.h soc/intel/cannonlake: Add/use enums for IGD config 2025-05-14 18:13:20 +00:00
chipset.cb soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree 2024-10-11 07:48:06 +00:00
chipset_pch_h.cb soc/intel/cannonlake: Hook up CNVi Bluetooth UPDs to devicetree 2024-10-11 07:48:06 +00:00
cnl_memcfg_init.c
cometlake_1_2.c
cpu.c soc/intel/adl to jsl: Explicitly include static.h for config_of_soc 2024-10-07 20:33:49 +00:00
elog.c
finalize.c soc/intel/adl to jsl: Explicitly include static.h for config_of_soc 2024-10-07 20:33:49 +00:00
fsp_params.c drivers/intel/fsp2_0: Add Kconfig to select FSP for BMP rendering 2025-05-08 16:51:25 +00:00
gpio.c
gpio_cnp_h.c
gpio_common.c soc/intel/adl to jsl: Explicitly include static.h for config_of_soc 2024-10-07 20:33:49 +00:00
graphics.c
gspi.c
i2c.c
Kconfig soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as appropriate 2025-08-02 01:46:21 +00:00
lockdown.c soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE 2025-03-10 15:19:26 +00:00
lpc.c soc/intel/adl to jsl: Explicitly include static.h for config_of_soc 2024-10-07 20:33:49 +00:00
Makefile.mk soc/intel/cannonlake: Drop redundant PcieRpEnable 2025-04-23 14:15:39 +00:00
nhlt.c
p2sb.c
pcie_rp.c soc/intel/cannonlake: Drop redundant PcieRpEnable 2025-04-23 14:15:39 +00:00
pmc.c soc/intel/adl to jsl: Explicitly include static.h for config_of_soc 2024-10-07 20:33:49 +00:00
pmutil.c soc/intel: Allow zero values for PMC GPE0 DW registers 2025-01-29 11:46:11 +00:00
reset.c
sd.c
smihandler.c
spi.c
systemagent.c soc/intel/adl to jsl: Explicitly include static.h for config_of_soc 2024-10-07 20:33:49 +00:00
uart.c
vr_config.c soc/intel/adl to jsl: Explicitly include static.h for config_of_soc 2024-10-07 20:33:49 +00:00
xhci.c