The ITE EC may take more than 2 seconds to complete EC FW
hash calculation in some corner cases. For example, boot with
a dead battery, EC even takes more than 10 seconds to complte
the hash calculation. Extend the timeout from 2 seconds to 12
seconds to cover the ITE EC cases, it should not impact boot
time and functionalities.
BUG=b:445034279, b:444392807
Change-Id: I4f6e23dc3096cbba04c33c8f3cc36c90aa83462a
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89293
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides `SkipExtGfxScan` UPD as the Fatcat device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.
TEST=Able to save ~10ms+ boot time on google/fatcat.
FSP FPDT Data is showing the timestamp between those function calls.
Without this patch:
50b8 680462 42 76f18bda-2195-4fb6-9a940e0bacdeecab
50b9 696649 16187 76f18bda-2195-4fb6-9a940e0bacdeecab
With this patch:
`CheckOffboardPcieVga` is not getting called.
Change-Id: I198a99ac5596ff98a9cc673dbd84889d7c5386cb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88888
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The multi-line `$(eval $(call ...))` for adding the default BMP logo
contained extraneous whitespace. This included a leading space before
`logo.bmp` and, more critically, a newline, tab, and non-breaking
spaces before `CONFIG_BMP_LOGO_FILE_NAME`.
This problematic whitespace was passed as part of the third argument
(`$(3)`) to the `add_bmp_logo_file_to_cbfs` macro. Inside the
macro, the deferred variable expansion `$$($(3))` would fail because it
was searching for a variable name with leading non-breaking spaces.
This resulted in the `logo.bmp-file` variable being set to an empty
string, causing a build failure when the cbfs tool tried to find the
logo file.
This commit collapses the function call onto a single line to remove
all line continuations and problematic whitespace, ensuring the
correct, clean arguments are passed to the macro.
BUG=b:444655145
TEST=Able to verify that 'logo.bmp' is added correctly to the CBFS,
and also verify the FW splash screen visible on redrix device.
Change-Id: Ia91b927dd0248909fc1c75534a7e7b00dab0fc09
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit addresses a potential low power state over-consumption
issue. This issue could arise if SPI DMA has been locked down while a
transfer was still marked as active, typically if a SPI DMA transfer
failed and hung.
The fast_spi_dma_lock() function now checks if a DMA transfer is ongoing
and ensures that it is marked as complete before locking the DMA control
register.
Change-Id: I5e08991b2160a43013b129d302c46fc229f2286d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88913
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit updates GPP_F17 (CODEC_INIT_N) configuration to fix an issue with the 3.5mm headphone jack on the I2S codec AIC not detecting headphone plug/unplug events.
Specifically, we need to configure GPP_F17 to have interrupt capability, edge detection to detect plug and unplug events, and power state persistence.
TEST=After booting to OS, plug and unplug a headphone to the I2S codec add-in card, headphone is getting detected.
Change-Id: I263f7e9e2da0440801404dddfcf534b9ea79d470
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Add H58G66CK8BX147 memory part as DRAM ID 2.
BUG=b:446088494
TEST=None
Change-Id: Ice18fd3209b0552be8f8612aaa3ff30ba76c8b83
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89269
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add H58GE6AK8BX104 memory part as DRAM ID 3.
BUG=b:445211686
TEST=None
Change-Id: I10876384f67d9201b14dc19213cfc77d62213070
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Add H58GE6AK8BX104 in the memory_parts.json and re-generate
the SPD.
BUG=b:445211686
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I4bf1d0fc3325ec2d4247a0263a44a81934a3a90e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
smbios_mainboard_enclosure_type() is not linked when SMBIOS
is disabled. Fixes a linker error when the user disabled SMBIOS
table generation in Kconfig.
Change-Id: Ic3e70c658d01a839eb37f0862f31ee9f65a84300
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89280
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The panel id is sampled with AUX_IN4 (PANEL_ID_LOW_CHANNEL) and AUX_IN5
(PANEL_ID_HIGH_CHANNEL). Introduce 3 voltage thresholds to distinguish
different panels:
- v < 0.5V -> id = 0
- 0.5V ≤ v < 1.0V -> id = 1
- v ≥ 1.0V -> id = 2
BUG=b:433405205
TEST=Tested by booting with the payload and confirming the kernel get
the correct skuid.
Change-Id: I590a19b6cade3cae15a58a9b3541ff471e038435
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89217
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure eMMC DLL tuning values for Kaladin project.
Sending different speed TX/RX command/data signal to eMMC and check the response is success or not.
Based on the test result from each eMMC source used in the project as the tuning value.
Refer to EDS-Vol2-42.3
BUG=b:440126134
TEST=Pass on 2500 cycle of cold boot stress on all eMMC sku
Change-Id: I6295b36500053356a28d51b48a9758ee32b82b53
Signed-off-by: Doris Hsu <doris.hsu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89034
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Add TM panel TM_TL121BVMS07_00C serializable data to CBFS.
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
The developer/recovery screen is not functional yet as the vendor is
still debugging it. This change is proposed to enable firmware build.
[INFO ] CBFS: Found 'panel-TM_TL121BVMS07_00C' @0x81f80 size 0x77
in mcache @0xfffdd540
BUG=b:428854543
TEST=build and check the CBFS include the panel
BRANCH=skywalker
Change-Id: I50e56aef1576722b7f2fb811c5d9df2a5697edae
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89216
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Due to a GPIO configuration issue, the buzzer continues to operate
after the OS boots, producing noise from the capacitor.
The buzzer is driven by the GPIO pin and P_MOS, so it should be set
to high in the coreboot.
For the schematics, please refer to b:442747023#comment4.
BUG=b:442747023
TEST=Can not hear abnormal noise.
Change-Id: I720e5cc0e8c499d654a2b3002c3647d37e2ae8d3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89035
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only need the first 512, so skip reading the rest to save
boot time. With 96GB, it reduces time in FSP-M from 906,307
to 326,302.
Change-Id: Ia226402fdf613ba4b851fa9c4c7d9354d599be7c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89220
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Select the newly introduced `HAVE_CBFS_FILE_OPTION_BACKEND` capability
for the Qualcomm x1p42100 SoC family.
This SoC is used in ChromeOS devices that rely on the CBFS file backend
to store and retrieve runtime configuration options (like the QCLib
configuration data). Selecting this capability ensures the correct
option backend is chosen in the Kconfig `Option backend to use` choice.
TEST=Build and boot a board using the x1p42100 SoC (e.g., bluey).
Confirm the `CONFIG_USE_CBFS_FILE_OPTION_BACKEND` option is enabled
in the build.
Change-Id: Ie0dee155a504da215669a79d7100cdbaf97d5261
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce a new static function, `qclib_debug_log_level`, that
checks a runtime-configurable option, "qclib_debug_level", to
control whether QCLib enables serial logging.
This allows for dynamic control of QCLib's verbose output via a
coreboot option instead of relying solely on the static
`CONFIG(CONSOLE_SERIAL)` Kconfig option. This is necessary because
while the serial console might be enabled for general coreboot
logging, the user may want to suppress the often extensive and
low-level output from QCLib to keep the console clean during normal
operations.
The check for enabling QCLib's serial output is updated from
`if (CONFIG(CONSOLE_SERIAL))` to
`if (CONFIG(CONSOLE_SERIAL) && qclib_debug_log_level())`
The option value is read using
`get_uint_option("qclib_debug_level", 1)`, meaning the default
behavior is to enable QCLib logging if `CONSOLE_SERIAL` is set,
maintaining backward compatibility unless the option is explicitly
set to 0 at runtime.
BUG=b:445211186
TEST=Build and boot a Qualcomm platform with CONFIG_CONSOLE_SERIAL
enabled. Confirmed QCLib logs are present by default.
Set option "qclib_debug_level" to 0 via CBFS option and confirmed
QCLib logs are suppressed while coreboot serial output remains
active.
Change-Id: I2c7326fae889508f09e1eb5e3863456cf54f5c29
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
As per Intel doc 861712, enable acoustic noise mitigation for fatcat,
disable fast PKG C state ramp and set slew rate to Fast/2 for VR
domain.
Reference: Intel doc 861712
TEST=Able to build and boot google/fatcat.
Before:
AcousticNoiseMitigation : 0x0
FastPkgCRampDisable for Index = 1 : 0x2
SlowSlewRate for Index = 1 : 0x0
After:
AcousticNoiseMitigation : 0x1
FastPkgCRampDisable for Index = 1 : 0x1
SlowSlewRate for Index = 1 : 0x0
Change-Id: I63c51354cb70c87f9c9c239cb56d5c64f0eabe32
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Because the touchpad includes two touch chips with the same I2C slave
address, the firmware configuration is used to differentiate them.
BUG=b:437025836
TEST=emerge-nissa coreboot
Change-Id: If1e414594a2866bdc122d48d5f3e2f36066cd3d5
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89106
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 2 touch panels GTH1563 and GTH7503
BUG=b:444136795
TEST=flash and boot on kaladin, execute evtest to see correct HID and
verify touch function works fine
Cq-Depend:chromium:6953071, chrome-internal:8592598
Change-Id: I9b33b5c8e216c5c8e7a6d9e38cd8d01b85dec67e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89187
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C in the
memory_parts.json and re-generate the SPD.
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I0db533908fbea2bc04a55191960aaeec8461f47d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Set the UPD `TcNotifyIgd` to `2` (Auto), so that the TCSS subsystem
will notify the Integrated Graphics of display changes.
Change-Id: I2b47a534f0816545fe58bde8963c56f0455871eb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89054
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new Kconfig option, `HAVE_CBFS_FILE_OPTION_BACKEND`, to
explicitly select the capability of using a CBFS file for option
storage.
This capability is currently only used by ChromeOS boards leveraging
FSP 2.0. By decoupling the capability check from the choice default
selection logic, we can simplify the configuration of the option
backend choice:
- The new capability config is set to 'y' only if `CHROMEOS &&
PLATFORM_USES_FSP2_0`.
- The 'Option backend to use' choice now depends on this new capability
config.
This change allows other SoC platforms beyond Intel to leverage this
feature.
TEST=Build all ChromeOS FSP 2.0 boards and confirm the default option
backend is still USE_CBFS_FILE_OPTION_BACKEND.
Change-Id: Ia55e0feae8fd462411ed3e9306d19ed6d1cfcaf1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add H58G66BK8BX067 memory part as DRAM ID 2.
BUG=b:445200980
TEST=None
Change-Id: Ica4c253ebed922f204e4782bbfeb1f09f12f5723
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Table is from vendor. Update HWEQ and AGC setting.
BUG=b:435345756
TEST=emerge-brox coreboot
check system audio output is fine
Change-Id: I0869a4902e38e8010274769de7f8e7b9a4160aae
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Disable eMMC related GPIO pins via firmware config on non-eMMC skus
BUG=b:443202137
TEST=flash and boot successfully on all kaladin SKU
Change-Id: Ia98702368208649fc0891417c7e8c6c3685d40be
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89069
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`dt_add_reg_prop` and the newly introduced `dt_add_iommu_addr_prop`
share identical logic for building the binary data buffer, differing
only in the property name written to the Device Tree. Therefore,
refactor the shared logic into a new static helper function,
`dt_add_addr_and_size_prop`.
The existing `dt_add_reg_prop` is converted to a wrapper around this new
helper.
`dt_add_iommu_addr_prop` is introduced as a separate wrapper to
specifically add the `iommu-addresses` property. This property defines
reserved IOVA ranges or identity-mapped regions, such as a display
framebuffer configured by the bootloader. It is typically utilized
within the `reserved-memory` subsystem.
BUG=b:435289727
TEST=The below translation fault does not occur.
[ 0.171028] arm-smmu-v3 30800000.iommu: TBU_id-2-fault_id:0x2000008(0x8), TF read in NORMAL world, iova:0xa3000000, sid:144, ssid:0, ssidv:0, secsidv:0
Change-Id: Icedcce5681a7b659b11b7e7208663bc1d920ce3b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89152
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Realtek ALC1320 as speaker Amplifier.
Use ALC721 as codec and ALC1320 as Amplifier on SoundWire Link 3.
BUG=b:442964982
TEST=emerge-fatcat coreboot
1.Set fw_config AUDIO bits to AUDIO_ALC1320_ALC721_SNDW
2.check the SSDT.dsl:
PCI0.HDAS.SNDW including 0x000331025D072101 & 0x000332025D132001
Change-Id: I4c6b5c3f2d9acb7eaf8f77844526bc9de3ae1f99
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89177
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the VNC18 regulator API for the MIPI panel usage.
BUG=b:432353024
BRANCH=skywalker
TEST=Use an oscilloscope to confirm that the regulator’s output
voltage is 1.8V.
Change-Id: Ib2065d8b4f92f4ad266976883cb2927107330a69
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89172
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To provide power to MIPI panel, add support for regulator VCN18.
BUG=b:432353024
BRANCH=skywalker
TEST=Use an oscilloscope to confirm that the regulator’s output
voltage is 1.8V.
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I4d90b3c053f1a06ae0c65d6ce6d800c22d6d3442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89171
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a flag "USE_SYSTEM_CMOCKA" in the Makefile of tests. (default 1)
If USE_SYSTEM_CMOCKA=1, we will check if the system has Cmocka module,
and link it directly. If the system doesn't have Cmocka, we will set the
flag to 0 and print a warning message.
If USE_SYSTEM_CMOCKA=0, we will build Cmocka from 3rdparty source code.
BUG=none
TEST=make unit-tests -j
TEST=USE_SYSTEM_CMOCKA=0 make unit-tests -j
BRANCH=none
Signed-off-by: roccochen@chromium.com <roccochen@chromium.org>
Change-Id: I091784ca541e2590e3db0a18ceea83e7895ed0c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79019
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use fw config bit 29 to identify different ish files in pujjolo
when ISH_PRESENT and pujjoquince when ISH_ABSENT.
ISH_PRESENT : pujjolo_ish.bin
ISH_ABSENT : lite_ish.bin
BUG=b:437881361
TEST=Build and boot to OS, check pujjolo and pujjoquince load
corresponding ish file using command ectool --name=cros_ish version and test warmboot/coldboot/suspend pass.
Change-Id: I61b90881abcad368dd668f2631f061b0ea00b57f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
GPP_B23 and GPP_A15 GPIOs in Felino design being used for MEM
straping selection but Felino supports only one mem id (index 0)
hence, these GPIO reads were never needed in felino code.
The GPP_A15 and GPP_B23 pins on the Fatcat mainboard variant Felino
are no longer used. Update the GPIO table to reflect this and
explicitly set the pins to not connected (NC) as per schematics
dated 08/30.
TEST=Able to build and boot google/felino.
Change-Id: I9d8ed19aab612f7104227544c24c37d19024cfb0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The GPP_A15 pin on the Fatcat mainboard variant Lapis is not used,
according to schematics dated 08/30.
Update the GPIO table to reflect this and explicitly set the pin to
not connected (NC).
TEST=Able to build google/lapis.
Change-Id: Ib89421952f5844283809fe99a902e36a17f55fae
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89154
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
These are not programmed by coreboot, so drop them.
Change-Id: If7b371aa6f64a7f034344a6e926ca0662fa717c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: Id3f870c531f0cfd078c899953ff65b406e7e5bb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89138
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are not programmed by coreboot, so drop them.
Change-Id: I1ad4f33565ce1d5a67ac7f066fd5140a7cb2faf8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: Ifdcbb52cf1823692296775895130fcec8be59c85
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: If1c68f183012d78b3e8847e8fe103280fe0103ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
These are not programmed by coreboot, so drop them.
Change-Id: I577634eef5e0f218be81323bbd5c6d8a0651549c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89134
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
