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soc/mediatek/common: Add support for regulator VCN18

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To provide power to MIPI panel, add support for regulator VCN18.

BUG=b:432353024
BRANCH=skywalker
TEST=Use an oscilloscope to confirm that the regulator’s output
voltage is 1.8V.

Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I4d90b3c053f1a06ae0c65d6ce6d800c22d6d3442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89171
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Vince Liu 2025-09-15 11:12:42 +08:00 • committed by Matt DeVillier
commit fe70426dd7
3 changed files with 45 additions and 0 deletions
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11
src/soc/mediatek/common/include/soc/mt6359p.h
View file

@ -35,12 +35,14 @@ enum {
PMIC_VSRAM_PROC1_ELR = 0x1b44,
PMIC_VSRAM_PROC2_ELR = 0x1b46,
PMIC_VSRAM_MD_ELR = 0x1b4a,
PMIC_VCN18_CON0 = 0x1c2e,
PMIC_VSIM1_CON0 = 0x1cd0,
PMIC_VM18_CON0 = 0x1d88,
PMIC_VSRAM_PROC1_VOSEL1 = 0x1e90,
PMIC_VSRAM_PROC2_VOSEL1 = 0x1eb0,
PMIC_VSRAM_MD_VOSEL1 = 0x1f36,
PMIC_VSIM1_ANA_CON0 = 0x1fa2,
PMIC_VCN18_ANA_CON0 = 0x2010,
PMIC_VM18_ANA_CON0 = 0x2020,
};
@ -68,6 +70,7 @@ enum {
MT6359P_VM18,
MT6359P_VMODEM,
MT6359P_VSRAM_MD,
MT6359P_VCN18,
MT6359P_MAX,
};
@ -78,6 +81,11 @@ enum {
#define VM18_VOL_REG_SHIFT 8
#define VM18_VOL_OFFSET 600
#define VCN18_VOL_UV_MAX 1900000
#define VCN18_VOL_UV_MIN 1800000
#define VCN18_VOL_MV_OFFSET 600
#define VCN18_VOL_SHIFT 8
#define EFUSE_WAIT_US 5000
#define EFUSE_BUSY 1
@ -90,9 +98,12 @@ void mt6359p_set_vm18_voltage(u32 vm18_uv);
u32 mt6359p_get_vm18_voltage(void);
void mt6359p_set_vsim1_voltage(u32 vsim1_uv);
u32 mt6359p_get_vsim1_voltage(void);
void mt6359p_set_vcn18_voltage(u32 vcn18_uv);
u32 mt6359p_get_vcn18_voltage(void);
void mt6359p_enable_vpa(bool enable);
void mt6359p_enable_vsim1(bool enable);
void mt6359p_enable_vm18(bool enable);
void mt6359p_enable_vcn18(bool enable);
void mt6359p_init_pmif_arb(void);
u32 mt6359p_read_field(u32 reg, u32 mask, u32 shift);
void mt6359p_write_field(u32 reg, u32 val, u32 mask, u32 shift);

1
src/soc/mediatek/common/include/soc/regulator.h
View file

@ -21,6 +21,7 @@ enum mtk_regulator {
MTK_REGULATOR_VSRAM_PROC11,
MTK_REGULATOR_VSRAM_PROC12,
MTK_REGULATOR_VRF12,
MTK_REGULATOR_VCN18,
MTK_REGULATOR_VCN33,
MTK_REGULATOR_VDD18,
MTK_REGULATOR_VIO18,

33
src/soc/mediatek/common/mt6359p.c
View file

@ -336,6 +336,34 @@ u32 mt6359p_get_vsim1_voltage(void)
return 1000 * (reg_offset + reg_vol + reg_cali);
}
u32 mt6359p_get_vcn18_voltage(void)
{
u32 reg_vol, reg_cali;
if (!pmif_arb)
die("[%s] ERROR: pmif_arb not initialized", __func__);
reg_vol = 100 * mt6359p_read_field(PMIC_VCN18_ANA_CON0, 0xF, VCN18_VOL_SHIFT);
reg_cali = 10 * mt6359p_read_field(PMIC_VCN18_ANA_CON0, 0xF, 0);
return 1000 * (VCN18_VOL_MV_OFFSET + reg_vol + reg_cali);
}
void mt6359p_set_vcn18_voltage(u32 vcn18_uv)
{
u32 reg_vol, reg_cali;
if (!pmif_arb)
die("[%s] ERROR: pmif_arb not initialized", __func__);
if (vcn18_uv < VCN18_VOL_UV_MIN || vcn18_uv > VCN18_VOL_UV_MAX) {
printk(BIOS_ERR,
"%s: VCN18 voltage %d is out of range (%d uV - %d uV)\n",
__func__, vcn18_uv, VCN18_VOL_UV_MIN, VCN18_VOL_UV_MAX);
return;
}
reg_vol = (vcn18_uv / 1000 - VCN18_VOL_MV_OFFSET) / 100;
reg_cali = (vcn18_uv / 1000) % 100 / 10;
mt6359p_write(PMIC_VCN18_ANA_CON0, (reg_vol << VCN18_VOL_SHIFT) | reg_cali);
}
void mt6359p_enable_vpa(bool enable)
{
mt6359p_write_field(PMIC_VPA_CON0, enable, 0x1, 0);
@ -351,6 +379,11 @@ void mt6359p_enable_vm18(bool enable)
mt6359p_write_field(PMIC_VM18_CON0, enable, 0x1, 0);
}
void mt6359p_enable_vcn18(bool enable)
{
mt6359p_write_field(PMIC_VCN18_CON0, enable, 0x1, 0);
}
void mt6359p_init_pmif_arb(void)
{
if (pmif_arb)