In order to bring the denver core complex up the MTS microcode
needs to be loaded. Include the MTS microcode in cbfs.
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and noted mts is in cbfs.
Change-Id: I863202b06a866a37073009364ddc0d929f5d6d46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205635
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
We suspect that the code was stuck on init pllx (PLLX - acts as a clock source
for the CPU cluster). So removing the init call for pllx. This needs to be added
later when required. Also added a few more printks to display the progress.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Print messages seen on serial console.
Change-Id: I70e908a9ce1f3598d68bda68c0401a78834597d1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/205680
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Pull in mainboard specific bootblock_init function from nyan into
rush. Additionally, pull in all files required for proper compilation of rush
after adding the bootblock_init function
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Change-Id: I69c736275f66eca3ad92f97d166e91d4c2301364
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/205583
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Enable adding of clock.c to romstage and ramstage in addition to bootblock. Code
for enabling armv8 core is not included yet. clock_init added to bootblock.c
BUG=None
BRANCH=None
TEST=Compiles successfully for rush.
Change-Id: I858c41a83d665da2c406707586b5e35a732177d4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/205581
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Define functions for setting cntfrq register in arm and arm64 arch. This allows
SoCs to set this register independent of the architecture being used.
BUG=None
BRANCH=None
TEST=Compiles successfully for nyan and rush
Change-Id: I93240419b2c012eee29a408deff34a42af943a63
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/205580
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
With the fix to the serial port address the bootblock size increased
which subsequently bumped the bct size because it works in blocks.
Another bump will be needed in the future once more code is added.
For the time being this should work.
BUG=chrome-os-partner:29882
BRANCH=None
TEST=Built and see serial output from bootblock.
Change-Id: I8a16e8faeb7223456286d2b14fd1cd2f78b00b71
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205436
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The version field for t132 cpus is 0x00130001. Update it to
the correct version.
BUG=chrome-os-partner:29882
BRANCH=None
TEST=Built and was able to see serial with subsequent changes.
Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205435
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Change Kconfig UART variable names to make them unique. Names used earlier were
conflicting with t124 names. Thus, UART_ADDRESS and others turned out to be
zero.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. bootblock prints message on serial console.
Change-Id: I221ef25e5bd2dc5d97928c2eaf4281ea7caf1403
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/205432
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
The actual storm device has a single USB interface, which needs to be
explicitly turned on using GPIO51.
BUG=chrome-os-partner:29871
TEST=verified that depthcharge finds and boots a kernel from USB stick
Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205329
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
When the IPQ SPI driver was ported to coreboot, a few GPIO related
definitions ended up in a wrong include file. Move them to the proper
place and get rid of duplicated definition of GPIO_OUT.
BUG=chrome-os-partner:27784, chrome-os-partner:29871
TEST=proto0 still boots with the new firmware
Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205328
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be
swapped with GPIO69
- Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD
- Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround
- In order to support both P2A and P2B with one firmware image we need
to read the EC board version and use the right SPD GPIO for bit3
- Touchpad I2C address changed to 0x4a/0x26
BUG=chrome-os-partner:29502
BRANCH=None
TEST=boot on P2A and P2B boards
Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Storm devices use more recent Spansion flash, add its description to
the table of supported devices.
BUG=chrome-os-partner:29871
TEST=the updated firmware boots all the way to depthcharge
Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/205182
Reviewed-by: Stefan Reinauer <reinauer@google.com>
The preboot MTS microcode needs to be supplied within the
bct so the BootROM can load it. The size of the bootblock
space in SPI needed to be extended to accomodate the extra
length.
BUG=chrome-os-partner:29059
BUG=chrome-os-partner:29060
BRANCH=None
TEST=Built rush with updated cbootimage with t132 support.
Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204940
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This adds a block in the SMI handler to call init functions for
drivers which may be used in SMM. A static variable is used to
ensure the init functions are only called once.
BUG=chrome-os-partner:29580
BRANCH=mccloud
TEST=Built and booted on mccloud, system no longer hangs when
pressing power button at the dev mode screen. Also tested on parrot.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee
Reviewed-on: https://chromium-review.googlesource.com/204764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable the ACPI Device for the EC ALS.
BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw
Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203744
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC can export ALS information if the sensor is attached
to it directly rather than to the host. This adds a basic
ACPI ALS device and implements the required information.
The kernel does not use the _ALR tuple set but it is required
by the ACPI spec so this just adds the sample two point
response curve defined in ACPI 5.0 section 9.2.5.
The EC does not currently send events for lux value changes so
a polling interval of 1 second is defined.
BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw
Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This makes it so that we always log the generic "system boot" event.
If boot count support has not been implemented, fake it.
BUG=chrome-os-partner:28772
BRANCH=nyan
TEST=booted on Big, ran "mosys eventlog list" and saw
"System boot" event logged with boot count == 0
Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204525
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add config option for customize this value by board.
BUG=chromium:366940
TEST=Manual add config for specific board and verify by dmidecode.
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I6deb7f07c00c899bad1eb08fa6a2410deb7a8c6a
Reviewed-on: https://chromium-review.googlesource.com/203657
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Kevin Cheng <kevin.cheng@intel.com>
Tested-by: Kevin Cheng <kevin.cheng@intel.com>
The GPIO controller (configured as IRQ14 by default) is level triggered
and active high according to documentation. At the moment it seems to
be misbehaving and firing constantly which is preventing package C-states
since one core is always busy servicing imaginary events.
Until this is understood and fixed don't report an interrupt for the GPIO
controller. Since there are 16 peripheral IRQ capable GPIOs this is not
used currently.
Also remove the hardcoded MADT IRQ override entry for IRQ14 since we are
using the GPIO controller in ACPI mode so it gets the interrupt
configuration from _CRS.
BUG=chrome-os-partner:29548
BRANCH=None
TEST=boot on wtm2 and check for package C-state entry with powertop
Change-Id: Ibf562fe3512e68d3944fda61a023a1631f7acd57
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203645
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Depthcharge clears up all unused DRAM before starting Linux, and does
not know the translation table location. Instead of adding an
exclusion term to the memory wipe descriptor lets move the table to
the top of IMEM, it is also likely to be a good location in the
future, when EFS is introduced.
BUG=chrome-os-partner:27782
TEST=manual
. built and ran firmware on ap148
Change-Id: I76546438d243076dda4d0eb3f784e0b5a8a1fa22
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203624
Reviewed-by: Julius Werner <jwerner@chromium.org>
For some panels, the plld can't provide the pixel clock that
the panels wants, so we give it a good enough one. And we
should calculate the dp/dc settings by the real pixel clock.
BRANCH=nyan
BUG=chrome-os-partner:29489
TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big).
No screen flicker is observed. No sor dp fifo underflow found.
Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203358
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add XN/PXN bits to prevent cpu from fetching speculative instructions
on noncacheable region.
BUG=chrome-os-partner:28568
BRANCH=nyan
TEST=Build and run reboot tests on nyan_big
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b
Reviewed-on: https://chromium-review.googlesource.com/203447
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Hynix 2GB/4GB configs have been fine-tuned.
Kingston 2GB config is new, uses RAMCODE 0x6.
BUG=none
TEST=emerge-nyan_big coreboot-nyan_big OK. Flashed to my
Big 2GB system (PVT1/SKU1) and it booted OK.
BRANCH=nyan_big
Change-Id: I8a23a5568ef84d5befc13623f78bce664130f314
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/203305
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch adds code to initialize the two DWC3 USB host controllers and
their associated PHYs to the IPQ806x SoC (closely imitating the existing
DWC3 implementation for Exynos5), and uses them to initialize USB on the
Storm mainboard.
BUG=chrome-os-partner:29375
TEST=Hack up netboot to get around missing SPI flash, load a file over
TFTP. Hack a storage read into the storage attach function, dump the
data and confirm that it looks right. Enable USB debugging and confirm
3.0 devices get enumerated at SuperSpeed (mostly).
Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202157
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
- Put SSD into reset on transition to S3/S5 to prevent leakage
- Fix GPIO number for wlan disable used in smihandler
- Enable generic hub driver in libpayload
- Fix comment in devicetree about S0ix
BUG=chrome-os-partner:28502
BRANCH=None
TEST=Build and boot on samus
Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203185
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
XHCI driver was not enabled in libpayload and some ports were
disabled that should be enabled.
The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to
properly indicate unused so crossystem does not attempt to
export GPIO number 255 in the kernel and trigger a warning.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2
Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Does not compile yet because tegra132 support is not present in cbootimage
BUG=None
BRANCH=None
TEST=Does not compile (Waiting for tegra132 support in cbootimage)
Change-Id: I796f171031bacf17106878d4a554e8f1cbfe93f8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/203145
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Changes might be required for .bct files as we get to know more.
Pulling in files from mainboard nyan for now
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Change-Id: Iaf81a384af0469c77940cf7309ba68018110b5eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/203144
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
CrOS devices with Chromeos EC need only use hostevent to communicate
recovery assertion to the BIOS. This CL removes wired GPIO from
determining recovery as it appears under certain conditions (cold
reset) the internal PU on the AP isn't strong enough and therefore the
value is sometimes seen as asserted.
BRANCH=none
BUG=chrome-os-partner:29333
TEST=compiles & BIOS no longer responds to rec_mode GPIO during boot.
Change-Id: Ib220cfa5f5bfe7193d555bfd32c0444b063d00f2
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202996
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
x86 systems run their romstage as execute-in-place from flash, which
prevents them from having writable data segments. In several code pieces
that get linked into both romstage and ramstage, this has been worked
around by using a local variable and having the 'static' storage class
guarded by #ifndef __PRE_RAM__.
However, x86 is the only architecture using execute-in-place (for now),
so it does not make sense to impose the restriction globally. Rather
than fixing the #ifdef at every occurrence, this should really be
wrapped in a way that makes it easier to modify in a single place. The
chromeos/cros_vpd.c file already had a nice approach for a wrapper
macro, but unfortunately restricted it to one file... this patch moves
it to stddef.h and employs it consistently throughout coreboot.
BRANCH=nyan
BUG=None
TEST=Measured boot time on Nyan_Big before and after, confirmed that it
gained 6ms from caching the FMAP in vboot_loader.c.
Change-Id: Ia53b94ab9c6a303b979db7ff20b79e14bc51f9f8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The recently introduced page table location value is wrong, it
overlaps with other areas of the code. This patch fixes the location,
a more robust scheme is needed for memory layout management.
BUG=none
TEST=manual
. occasional random failures disappear after this patch is applied
Change-Id: Idc9047d38712736c5e8197e933c373488b333649
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202641
Reviewed-by: Julius Werner <jwerner@chromium.org>
This is an interim change (before EFS is enabled), align ROM and RAM
stages so that they have enough room and do not step over each other.
BUG=chrome-os-partner:27784
TEST=manual
. booted coreboot successfully on ap148
Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202046
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
The driver as it was copied from u-boot provided a function to
transmit multiple characters in one invocation. This feature was not
ported to coreboot, there is no need to maintain the complexity when
only one character at a time is transmitted. It is also very desirable
to get rid of a 1024 byte array allocated on the stack.
The array was necessary to allow to convert multiple newline
characters in the transmit data flow into two character sequences
CRLF. Now just a single word is enough to keep one or two characters
to transmit.
BUG=chrome-os-partner:27784
TEST=verified that coreboot with the new code prints generates console
output.
Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201782
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Both DDI ports may be used on this board so it needs to be
able to detect a device on either port.
BUG=chrome-os-partner:28234
TEST=None (needs hardware)
Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202358
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The ME debug info is not compiled in when the loglevel is
turned down to save the space of all the strings so the
contents in me_status.c should not be included either.
BUG=chrome-os-partner:28234
TEST=Build and boot with LOGLEVEL=BIOS_ERROR
Change-Id: Ibef46d0da038e13b0de0a29ab038ab6fce395730
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202357
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Enable the option to always load the VBIOS even when not executing
- If the option rom is not executed then DDI-A needs to be enabled
for the internal panel to work when the kernel comes up.
BUG=chrome-os-partner:28234
TEST=Build and boot with working OS graphics in normal mode.
Change-Id: I4ebfbf9d8714490dfd2dc2e634928c449719a2bf
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Define a base address for page table entries. Place it 64KB below the
bootblock loading address.
BUG=chrome-os-partner:28467
TEST=verified that the page tables are being populated at this
address. Also observed that the SPI driver takes 900 ns to
process a byte as opposed to 1.5 us in case caching is not
enabled.
Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7
Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200332
This change updates the cfg file for Hynix/Micron/Samsung 4GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/202059
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU
BUG=chrome-os-partner:28234
TEST=Boot on P1.9
Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201083
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
