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wtm2: Fix issues with USB in firmware

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XHCI driver was not enabled in libpayload and some ports were
disabled that should be enabled.

The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to
properly indicate unused so crossystem does not attempt to
export GPIO number 255 in the kernel and trigger a warning.

BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2

Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-06-10 10:03:22 -07:00 • committed by chrome-internal-fetch
commit 328362469b
3 changed files with 11 additions and 10 deletions
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9
payloads/libpayload/configs/config.fox_wtm2
View file

@ -61,15 +61,16 @@ CONFIG_LP_TIMER_RDTSC=y
# CONFIG_LP_SPEAKER is not set
# CONFIG_LP_STORAGE is not set
CONFIG_LP_USB=y
CONFIG_LP_USB_UHCI=y
CONFIG_LP_USB_OHCI=y
CONFIG_LP_USB_EHCI=y
# CONFIG_LP_USB_XHCI is not set
# CONFIG_LP_USB_UHCI is not set
# CONFIG_LP_USB_OHCI is not set
# CONFIG_LP_USB_EHCI is not set
CONFIG_LP_USB_XHCI=y
CONFIG_LP_USB_HID=y
CONFIG_LP_USB_HUB=y
CONFIG_LP_USB_MSC=y
CONFIG_LP_USB_PCI=y
CONFIG_LP_USB_GEN_HUB=y
# CONFIG_LP_USB_MEMORY is not set
# CONFIG_LP_BIG_ENDIAN is not set
CONFIG_LP_LITTLE_ENDIAN=y
CONFIG_LP_IO_ADDRESS_SPACE=y

6
src/mainboard/intel/wtm2/acpi/chromeos.asl
View file

@ -18,7 +18,7 @@
*/
Name(OIPG, Package() {
Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery
Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer
Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect
Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery
Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer
Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect
})

6
src/mainboard/intel/wtm2/pei_data.c
View file

@ -47,11 +47,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
USB_PORT_FRONT_PANEL);
pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP,
USB_PORT_FRONT_PANEL);
pei_data_usb2_port(pei_data, 7, 0x40, 0, USB_OC_PIN_SKIP,
pei_data_usb2_port(pei_data, 7, 0x40, 1, USB_OC_PIN_SKIP,
USB_PORT_FRONT_PANEL);
pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
}