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arm: lpae: Set XN and PXN bits for noncacheable regions

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Add XN/PXN bits to prevent cpu from fetching speculative instructions
on noncacheable region.

BUG=chrome-os-partner:28568
BRANCH=nyan
TEST=Build and run reboot tests on nyan_big

Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>

Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b
Reviewed-on: https://chromium-review.googlesource.com/203447
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Jimmy Zhang 2014-06-06 17:00:10 -07:00 • committed by chrome-internal-fetch
commit c3d585bdfc
1 changed files with 3 additions and 2 deletions
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5
src/arch/arm/armv7/mmu.c
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@ -42,7 +42,7 @@
/* See B3.6.2 of ARMv7 Architecture Reference Manual */
/* TODO: Utilize the contiguous hint flag */
#define ATTR_BASE (\
0ULL << 54 | /* PN. 0:Not restricted */ \
0ULL << 54 | /* XN. 0:Not restricted */ \
0ULL << 53 | /* PXN. 0:Not restricted */ \
1 << 10 | /* AF. 1:Accessed. This is to prevent access \
* fault when accessed for the first time */ \
@ -51,7 +51,8 @@
0 << 1 | /* block/table. 0:block entry */ \
1 << 0 /* validity. 1:valid */ \
)
#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2))
#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2) | \
(1ULL << 53) | (1ULL << 54))
#define ATTR_WT (ATTR_BASE | (MAIR_INDX_WT << 2))
#define ATTR_WB (ATTR_BASE | (MAIR_INDX_WB << 2))