This code was left over from U-Boot and was superceded by the MCT.
BUG=chrome-os-partner:19420
TEST=Built and booted on snow.
BRANCH=None
Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63778
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This functions are by definition changing the data pointed to by their
arguments, so they shouldn't by const.
BUG=chrome-os-partner:19420
TEST=Built for snow.
BRANCH=None
Change-Id: Id29b3f76526aba463f8bb744f53101327f9c7bde
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63777
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
That symbol isn't used by anything and doesn't appear in other linker scripts.
BUG=chrome-os-partner:19420
TEST=Built for snow.
BRANCH=None
Change-Id: Iab54ecb3be2e262d7674ef8ee7ed13ea2e5b56f3
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63776
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
SATA is routed to PIRQG which should be interrupt 22
and not interrupt 21. The kernel uses MSI with this
device so this is only seen when booting with pci=nomsi
BUG=none
BRANCH=falco,peppy
TEST=manual: boot kernel with pci=nomsi
Change-Id: Ic90ca2c561fc4c53ec1d395c05872222c65ff98a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63796
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code generally intended to make the pointer const instead of the thing it
pointed at, but it had const backwards. Sometimes both the pointer and the
data could be const, but sometimes there were writes where only the pointer
should be.
BUG=chrome-os-partner:19420
TEST=Built for snow.
BRANCH=None
Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63775
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
When we go through the resume path, there shouldn't ever be a need to
initialize the PS/2 keyboard. The OS is going to reinitialize it
anyway, and it just slows the resume.
BUG=chrome-os-partner:20758
TEST=Verified Code flow in normal boot/S3 resume with print statements.
Verified Keyboard was correctly disabled and flushed by booting
to recovery mode screen while pressing keys on the integrated
keyboard.
BRANCH=none
Change-Id: I48bdca2fa2cc0c965401d10fef75cadb09d2e1e9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Add a function to disable and clear the keyboard controller.
BUG=chrome-os-partner:20758
TEST=Verified Code flow in normal boot/S3 resume with print statements.
Verified Keyboard was correctly disabled and flushed by booting
to recovery mode screen while pressing keys on the integrated
keyboard.
BRANCH=none
Change-Id: I3e1f011c3436fee5ce10993c6c26a3c8597c6fca
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63627
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
This also adds an option -x/--hexdump to dump the whole
CBMEM area for debugging.
BRANCH=none
BUG=chrome-os-partner:18637
TEST=cbmem -l works on snow
Change-Id: I244955394c6a2199acf7af78ae4b8b0a6f3bfe33
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62287
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
... and move the Kconfig variable from cpu/x86/Kconfig to cpu/Kconfig
Despite calling romstage memory CAR in this case, the variables actually
do live in SRAM on the Exynos CPUs. However, in order to share as much
generic code as possible, we're using the same infrastructure here.
BRANCH=none
BUG=chrome-os-partner:18637
TEST=none
Change-Id: I85173c37099a25f3e55980e88120401826cdf29c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
- prints hex and ascii
- detects duplicate all zero lines
BUG=none
TEST=none
BRANCH=none
Change-Id: I084b3072bc05725b23c5c3ca0dbf1533f164a08c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63660
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
... In order to do this, the graphics memory has to move into
the resource allocator and out of CBMEM.
BUG=chrome-os-partner:18637
BRANCH=none
TEST=none
Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63657
Reviewed-by: David Hendricks <dhendrix@chromium.org>
- prints hex and ascii
- detects duplicate all zero lines
BUG=none
TEST=none
BRANCH=none
Change-Id: I557fed34f0f50ae256a019cf893004a0d6cbff7c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62655
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
... In order to do this, the graphics memory has to move into
the resource allocator and out of CBMEM.
BUG=chrome-os-partner:18637
BRANCH=none
TEST=none
Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59326
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When the edid data structure changed a while ago, it caused hangs on snow
which were fixed by adding those missing members. Unfortunately we didn't
realize that pit needed the same fix.
BUG=chrome-os-partner:19420
TEST=Built and booted into recovery mode on pit. Saw that the video code no
longer hangs during initialization.
BRANCH=None
Change-Id: I81780b8135b99b2e24af723e703b9befff7b5ef0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63646
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
and add an ARMv7 version.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=chrome-os-partner:18637
TEST=no functional change
BRANCH=none
Change-Id: I13d9194235bf03e3cceb862c791572f89196b65b
Reviewed-on: https://gerrit.chromium.org/gerrit/59293
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
set_gpio() has a void return. Don't return a value from it.
BUG=None
BRANCH=None
TEST=Quick build.
Change-Id: Ib30eaac9cc645f47702093958b698bcfdcd64b9e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63599
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
An issue was observed using a specific vendor's TPM in that it
chokes on access to registers that are not explicitly defined in the
PC client specification. The previous driver used generic access
functions for reading and writing registers. However, issues come
to play when reading from the status register. It read it as a 32-bit
value, but that read address 0x1b which is not defined in the spec.
Instead of using generic access functions for the tpm registers
provide explicit ones. To that end provide more high level wrapper
functions to perform the semantic access required.
BUG=chrome-os-partner:20565
BRANCH=None
TEST=Built and booted on bolt. TPM access works through coreboot.
Change-Id: I781b31723f819e1387d7aa25512c83780ea0877f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63243
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The cache.h header uses standard int types but doesn't include stdint.h itself.
BUG=chrome-os-partner:19420
TEST=Built for pit.
BRANCH=None
Change-Id: If470978164b0cd1f05c27c2c8eda365133cc47ff
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63190
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
That speed is used with U-Boot instead of the more conservative 500 KHz.
BUG=chrome-os-partner:19420
TEST=Built and booted on pit.
BRANCH=None
Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63193
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Some registers and bit fields were wrong, but the difference is mostly
academic since the code that uses them are never called.
BUG=chrome-os-partner:19420
TEST=Built and booted on pit.
BRANCH=None
Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63189
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The divisor mask had been set to 0xff, but the bitfield is 4 bits wide.
BUG=chrome-os-partner:19420
TEST=Built and booted into RW on pit. A hang still prevents booting, but the
EC RW was updated successfully.
BRANCH=None
Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
When the board is in S3 and S5 the WLAN_DISABLE_L signal
can leak power into the WLAN power well since the GPIO
controlling WLAN_DISABLE_L is in the suspend well. Therefore,
drive WLAN_DISABLE_L low to avoid the power leak.
This is a clone of a Falco change:
I1a0df80dd47fdbd535aca7a9d49253794c480606.
BUG=chrome-os-partner:21291.
TEST=Manual. WLAN continues to work in S0.
Change-Id: I625dfbb228d1f293b880a52dfe552842d55a17d1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63220
Reviewed-by: Dave Parker <dparker@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
pixel_clock and link_clock.
Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively.
Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively.
Calculations are based on the intel_link_compute_m_n from linux kernel.
Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to
hard-coded value.
Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e
Reviewed-on: https://gerrit.chromium.org/gerrit/62915
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This code is left over from what the VBIOS did; It is redundant.
BUG=None
TEST=Build and boot on falco (equivalent to slippy)
BRANCH=None
Change-Id: I321c867c81ec8b4d5e10f8b51b872cecb3082d97
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/62290
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
The EHCI driver defines a maximum transfer timeout of two seconds. The
comments state that during tests the maximum amount of required transfer
time was for the SCSI TEST_UNIT_READY command on certain devices. We
have now observed a USB device (Patriot Memory 13fe:3100) that can NAK
this command for slightly more than two seconds. It will also completely
fail if the timeout hits, since it gets confused by the subsequent CSW
retry/recovery mechanism and starts producing babble errors. This patch
increases the timeout to three seconds to circumvent this problem.
BUG=chrome-os-partner:20988
TEST=Boot a Falco from a red-black RageXT USB stick.
Change-Id: I3c4fef468fb16eacc5a487d76d025a78fb450e27
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63095
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Since these boards do not support C10 we should not bother
advertising that state in the ACPI _CST.
Instead use this map:
ACPI(C1) = MWAIT(C1E)
ACPI(C2) = MWAIT(C3)
ACPI(C3) = MWAIT(C7S)
BUG=chrome-os-partner:21215
BRANCH=falco
TEST=manual: emerge-falco chromeos-coreboot-falco
Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62898
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The management engine is occasionally hanging the system on resume
when it is accessed. Since we actually don't need to do anything
with it on resume it can be disabled early in the resume path and
avoid assigning resources just to remove them later.
BUG=chrome-os-partner:19980
BRANCH=falco
TEST=manual: suspend/resume on falco and check /sys/firmware/log
to ensure that device 00:16.0 is disabled early and that no
resources are probed or assigned and that the device init path
does not execute.
Change-Id: I35573681e3a1d43d816d24954842cbe9c61f3484
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The management engine is slow, requiring at least 500ms between
when the Dram Init Done message is sent (right after memory training)
to when the MBP will report that it is successfully cleared and
that the ME can finally be sent the EOP message.
Currently this is adding 100-150ms to the boot time. If we defer
waiting for the MBP Clear indicator until the finalize step we
can gain back that lost time.
BUG=chrome-os-partner:19933
BRANCH=falco
TEST=manual: boot on falco with SMI debugging enabled to
ensure that the ME is locked down in the finalize step:
Finalizing Coreboot
SMI# #0
SMI_STS: PM1 APM
ME: MBP cleared
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are specific programming requirements for the usb3 ports
on all LynxPoint chipsets when transitioning to D0 or D3.
LynxPoint-LP has additional workaround steps needed involving
resetting the disconnected ports when transitioning to D0.
The workarounds are implemented in ACPI code so the controller
can transition properly into D3 at runtime.
BUG=chrome-os-partner:19975
BRANCH=falco
TEST=manual: 10000 suspend/resume cycles on falco devices
Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit ff81f50f0e.
Deferring this step until the finalize stage will allow us
to defer waiting for the MBP clear indicator and speeding
up the boot.
BUG=chrome-os-partner:19933
BRANCH=falco
TEST=manual: emerge-falco chromeos-coreboot-falco
Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559
Reviewed-on: https://gerrit.chromium.org/gerrit/62631
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory
layout, remove it from current configurations.
BUG=none
TEST=emerge-peach_pit chromeos-coreboot-peach_pit
BRANCH=none
Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b
Reviewed-on: https://gerrit.chromium.org/gerrit/61853
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back
that we need.
There are two new files for slippy annotated with comments about how it needs to evolve.
That said, this code has been tested on 3 different panels. Both dev and non-dev usages work.
physbase initialization to static value removed.
Moved spin calls to intel_dp_*
BUG=None
TEST=build and boot do MAINBOARD_DO_NATIVE_VGA_INIT enabled. Test in both dev and normal, with 3 different panels.
BRANCH=None
Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61136
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Peppy SPD table has 4GB configurations followed by 2GB configurations.
Current implementation does remapping to point 2GB configuration to the
same SPD index as the 4GB. This is different than Falco, which simply
duplicates the SPD data for all configurations. To simplify probing in
mosys, copy the Falco implementation of duplicating SPD data.
BUG=chrome-os-partner:20891.
TEST="mosys memory spd print all" on 2GB Falco, verify data is correct.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Idb185a437f3cf4f40d2dae1ae59c30235df8f489
Reviewed-on: https://gerrit.chromium.org/gerrit/61847
Reviewed-by: Dave Parker <dparker@chromium.org>
Reviewed-by: Jay Kim <yongjaek@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
When using RW firmware path the proper recovery reason can
be retrieved from the shared data region. This will result
in the actual reason being logged instead of the default
"recovery button pressed" reason.
BUG=chrome-os-partner:20788
BRANCH=falco
TEST=manual:
1) build and boot on falco
2) crossystem recovery_request=193
3) reboot into recovery mode, check reason with <TAB>
4) reboot back into chromeos
5) check event log entry for previous recovery mode:
25 | 2013-07-15 10:34:23 | Chrome OS Recovery Mode | Test from User Mode
Change-Id: I6f9dfed501f06881e9cf4392724ad28b97521305
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61906
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC temperature sensors were renumbered and now PECI
is at index 0.
BUG=chrome-os-partner:20432
BRANCH=falco
TEST=manual:
1) boot on falco
2) check /sys/class/thermal/thermal_zone0/temp
3) check 'temps' on ec console
Change-Id: Idde1457c42c80850b5b8ac22781060ed9b224d13
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61896
This may need further tuning but will start at 1.0%.
BUG=chrome-os-partner:20924
BRANCH=falco
TEST=manual: boot on falco and check /sys/firmware/log
localhost ~ # grep RTD2132 /sys/firmware/log
RTD2132: Enable 1.0% Spread Spectrum
I2C: 01:35 (Realtek RTD2132 LVDS Bridge)
Change-Id: I96e1c14dbc6a7bfaf1c8deb1806c48bf2fd3e32a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61895
This driver allows the mainboard to enable spread spectrum
clocking at 0.5%, 1.0%, and 1.5% with devicetree settings.
BUG=chrome-os-partner:20924
BRANCH=falco
TEST=emerge-falco chromeos-coreboot-falco
Change-Id: I59c61e67aa8e951fd9904ad951deb6d0ba29669e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61894
This is needed for SMBUS drivers to write to devices.
It was copied from existing intel southbridge driver.
BUG=chrome-os-partner:20924
BRANCH=falco
TEST=emerge-falco chromeos-coreboot-falco
Change-Id: Id0ce2393b2946a9c741413bca563a1a4dc0a4f5e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61893
The PWM is controlled externally from the APU.
BUG=None
TEST=It builds.
BRANCH=None
Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61513
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
What gets written into the parade is highly mainboard-dependent.
So the parade_writes array needs to be there.
BUG=None
TEST=build it, then ship it.
BRANCH=None
Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61486
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
The drivers in the kernel expect the devices using gpios
to generate interrupts to be edge sensitive. Make it so.
BUG=None
BRANCH=None
TEST=Built and booted. Devices continue to work.
Change-Id: I920ef621682d33ba081f737e97f0239f903db2f7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61678
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The drivers are designed to work with an edge triggered interrupt.
BUG=chrome-os-partner:20811
BRANCH=none
TEST=manual: ensure trackpad still works and cyapa interrupt
rate when holding a finger on the trackpad is lower.
Change-Id: I35a121ecfb6409bb9049f4d1e034185bb3bb7557
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61664
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=None
TEST=Built and booted on Snow.
BRANCH=None
Change-Id: I0f27bca119a248e22b06b7343ddc6a4cb85f68a0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/61532
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The 5250 DRAM code is *really* chatty. That's not a great
idea in time critical code, and DRAM init is generally
very sensitive about such things.
Finally, for those things that are errors, print them
at an error level, not a debug level.
BUG=chrome-os-partner:19420
BRANCH=none
TEST=not yet
Change-Id: Ifa86b019dfd5f8ae6c8a1da2a35b5d0808dc3623
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60100
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
When the board is in S3 and S5 the WLAN_DISABLE_L signal
can leak power into the WLAN power well since the GPIO
controlling WLAN_DISABLE_L is in the suspend well. Therefore,
drive WLAN_DISABLE_L low to avoid the power leak.
BUG=chrome-os-partner:20793
BRANCH=None
TEST=Manual. Checked the WLAN_DISABLE_L signal on wlan connector in both S3 and
S5. It is driven to ground. WLAN continues to work in S0.
Change-Id: I1a0df80dd47fdbd535aca7a9d49253794c480606
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61421
The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".
To prevent confusion, we should rename the constants to "RESET_ENABLE" and
"RESET_DISABLE".
BUG=none
TEST=emerge-daisy chromeos-coreboot-snow
BRANCH=none
Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
Reviewed-on: https://gerrit.chromium.org/gerrit/61081
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
