erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

pit: Bump the EC SPI bus speed up to 5 MHz.

Browse source 
That speed is used with U-Boot instead of the more conservative 500 KHz.

BUG=chrome-os-partner:19420
TEST=Built and booted on pit.
BRANCH=None

Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63193
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-07-24 06:18:20 -07:00 • committed by ChromeBot
commit 9362545695
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/pit/romstage.c
View file

@ -126,7 +126,7 @@ static void setup_ec(void)
{
/* SPI2 (EC) is slower and needs to work in half-duplex mode with
* single byte bus width. */
clock_set_rate(PERIPH_ID_SPI2, 500000);
clock_set_rate(PERIPH_ID_SPI2, 5000000);
exynos_pinmux_spi2();
}