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exynos5420: Fix some clock settings.

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Some registers and bit fields were wrong, but the difference is mostly
academic since the code that uses them are never called.

BUG=chrome-os-partner:19420
TEST=Built and booted on pit.
BRANCH=None

Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63189
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-07-24 03:57:49 -07:00 • committed by ChromeBot
commit 63fe4d864d
1 changed files with 4 additions and 7 deletions
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11
src/cpu/samsung/exynos5420/clock.c
View file

@ -41,9 +41,9 @@ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
{12, 16, 24},
{-1, -1, -1},
{16, 0, 8}, /* PERIPH_ID_SROMC */
{20, 16, 24},
{24, 0, 8},
{0, 0, 4},
{20, 20, 24},
{24, 24, 8},
{28, 28, 4},
{4, 12, 16},
{-1, -1, -1},
{-1, -1, -1},
@ -170,12 +170,9 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
break;
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(&clk->clk_src_peric1);
div = readl(&clk->clk_div_peric1);
break;
case PERIPH_ID_SPI2:
src = readl(&clk->clk_src_peric1);
div = readl(&clk->clk_div_peric2);
div = readl(&clk->clk_div_peric1);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4: