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lynxpoint: power management setup tweak

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Updated from 161 ref code

BUG=chrome-os-partner:20972
BRANCH=falco
TEST=emerge-falco chromeos-coreboot-falco

Change-Id: I3e07935fec1df21f14d97d165792fe54bf9e474c
Reviewed-on: https://gerrit.chromium.org/gerrit/62128
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Duncan Laurie 2013-07-16 09:01:43 -07:00 • committed by ChromeBot
commit 4e72de6221
1 changed files with 2 additions and 3 deletions
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5
src/southbridge/intel/lynxpoint/lpc.c
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@ -474,13 +474,12 @@ static void enable_lp_clock_gating(device_t dev)
* RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
* RCBA + 0x2614[23:16] = 0x20
* RCBA + 0x2614[30:28] = 0x0
* RCBA + 0x2614[26] = 1 (IF B2 STEP && 0:31.0@0xFA > 4)
* RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
*/
RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500);
/* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */
if (pch_silicon_revision() >= LPT_LP_STEP_B2 &&
pci_read_config8(dev, 0xfa) > 4)
if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b)
RCBA32_OR(0x2614, (1<<26));
RCBA32_OR(0x900, 0x0000031f);