Add ddr3-samsung-2GB config and modify 533mhz linit.
Support ddr3 freq up to 800mhz.
Enable ODT at LPDDR3.
BUG=None
TEST=Boot Veyron Pinky
Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/220113
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Lin Huang <hl@rock-chips.com>
Commit-Queue: Julius Werner <jwerner@chromium.org>
This gives the EC some time to wake-up between asserting /CS and
starting a transfer.
BUG=chrome-os-partner:32223
BRANCH=none
TEST=verified ~100us delay using logic analyzer on Pinky
Change-Id: I9874e65abd405874c43c594d8caeeff9e1300455
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220243
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Commit-Queue: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
This patch adds support for the board changes in rev2 (board_id = 0001).
It also moves the existing mainboard.c code around a bit to group it by
component.
BUG=chrome-os-partner:32139
TEST=Booted on rev1. Confirmed SD card still works. Confirmed power
button was still as broken as before.
Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220251
The static gpio_t initializers are stylish, but they are still a little
too annoying to write and read in day-to-day use. Let's wrap that in a
macro to make it a little easier to handle.
BUG=None
TEST=None
Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220250
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This adds a mainboard-specific bootblock function that will be used
to set up some board-specific parameters which are currently set up
in the SoC bootblock function.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ibee7076ebd6080f04b0697067e85ce8b6b2230e4
Reviewed-on: https://chromium-review.googlesource.com/220399
Reviewed-by: Julius Werner <jwerner@chromium.org>
Danube has become Pistachio, let's rename all instances where this SOC
is mentioned.
BUG=none
TEST=board urara still builds
Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220401
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
The codec interrupt needs to come from codec GPIO1, so use the
HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The
This means codec interrupt is GPIO46 which is PIRQO and should be
interrupt 30.
Also add GPIO defines for the GPIOs attached to the codec itself.
These are defined by index, and I used the same "jack detect" and
"mic present" indices that were used in baytrail.
The codec interrupt to the host is added at index 2 and the
hostword detect interrupt to the host is added at index 3.
These can be changed as we work through the implementation in the
kernel driver.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=build and boot on samus
Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220326
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move _PRW to the ACPI devices for the touchpad and touchscreen.
Add a _DSW method, but disable it by default for now until a
spurious wake issue can be resolved.
BUG=chrome-os-partner:32232
BRANCH=samus
TEST=build and boot on samus, ensure trackpad does not
spuriously wake the system.
Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220325
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the new battery status event to the SCI list so the
host can get notified when battery charge status changes.
BUG=chrome-os-partner:32196
BRANCH=auron
TEST=emerge-auron coreboot
Change-Id: Icc6182e65eb3a1d37442d3c0de1555b9ac2a2765
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220322
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Define specific GPIOs in gpio.h instaed of smihandler.c
- Add battery status event to SCI list
- Remove old proto board version defines and SPD index usage
- Do not disable cmd_pwr training now that it works on EVT board
BUG=chrome-os-partner:32196,chrome-os-partner:29117
BRANCH=samus
TEST=build and boot on samus
Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220321
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Auron/Peppy use GPIO 12 and GPIO 25 as wake up pins. GPIO_OWN,
GPIO_ROUTE, GPnCONFIG registers are setup if _DSW methods
are available.
Example capture after GPIO 12 and 25 are enabled for wake up:
GPIO Registers: GPIO_OWN_0 3dfbea0f GPIO_ROUTE_0 00000000
GPIO Registers: GPnCONFIGA_12 4000000d GPnCONFIGB_12 00000000
GPIO Registers: GPnCONFIGA_25 4000000d GPnCONFIGB_25 00000000
As Duncan suggested, I moved _PRW and _DSW to respective trackpad
and touch screen devices, and wake up worked with latest Chrome
image R39.6301.
Trackpad wake up is automatically enabled after boot. But touch
screen wake up is not enabled by powerd on boot.
BUG=chrome-os-partner:32047
TEST=check if trackpad can wake up board
Change-Id: Idd1e93dee8678044a6756cf36e8fdf4d27cd9676
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219906
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Copied dlaurie's entry from Rambi board. On Auron/Peppy
board, IRQ is hooked to GPIO 51. Based on table 5-36, this
is PIRQT. Then based on table 5-12, this is IRQ #35.
Thanks to Duncan for the pointer!
BUG=chrome-os-partner:32237
TEST=check if ALS is found by the kernel
Change-Id: I97bd932b48a6512632ee747715926a5761a7aeca
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219631
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
There's no need to add DMA ranges for these boards as
that memory is allocated within dpethcharge now. Additionally,
the DRAM_DMA_* Kconfig options were removed resulting in 0
values.
BUG=None
TEST=Built rush and ryu.
BRANCH=None
Change-Id: I52bb8f760a56226c75611f7981570a44d56f242e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219710
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Do the absolute minimum needed to allow the DPAUX mux ctl write
for I2C6. This leaves HOST1X off (reset and clock disabled) to
avoid a conflict with any kernel display driver init.
I2C6 init/enable will be moved to ramstage in the next CL.
BUG=chrome-os-partner:31820
BRANCH=none
TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good.
Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/218900
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
mosys will use this field to identify system
BRANCH=none
BUG=chromium:359155
TEST=build ok, make sure mosys can be executed on Auron
use dmidecode to check data is written correctly
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I597e78251250e26c02b13636e9a220a150dfa6ce
Reviewed-on: https://chromium-review.googlesource.com/217493
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
In order to not break FAFT, and to have a quicker recovery
mode boot, reboot the PD controller into RO image in romstage.
This is done before the EC since rebooting the EC into RO will
also reboot the host.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=boot samus EVT into recovery with 'dut-control power_state:rec'
and ensure that the PD controller is rebooted to RO in romstage.
Change-Id: I633f51afc382a7faab825c15618c0bc7566c4395
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Rk808 PMIC is a part that will probably be used by most Rk3288
boards, so it makes sense to keep it as common code in the the SoC
directory. This patch puts LDO control functions into rk3288/rk808.c, so
that the mainboard only has to call a simple interface to set up the
specific LDOs it requires.
BUG=chrome-os-partner:30167
TEST=Booted both this and the old version with a stubbed-out
i2c_writeb(), ensured that the final values are the same.
Change-Id: Ic172f9c402e829995f049726d3cb6dbd637039d1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217598
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the generic spintable support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=None
Change-Id: Ic9949144ed1e9a952290d50b6726bf5891547896
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218657
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
With the generic spintable support in place, use that.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Booted into kernel.
Change-Id: Id0832a4553101a366f011099e0744f6630d91924
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/218656
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Rush builds were throwing a _sync_sp_el0 exception due
to commit 65af2f3d (tegra132: support arm64 SMP bringup).
Fixed by copying over the rush_ryu devicetree.db, which
adds all the CPUs to the device tree. Basically the same
as commit 8f61ca2da but for rush.
BUG=None
BRANCH=None
TEST=Booted rush OK, brought up rush kernel from USB.
Change-Id: Ic9e34494ec8e6ad82e6020df6ad6fecd8763ac7e
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/217792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over
the bootblock, then exits to the romstage. this is necessary for some SOC
(e.g. tegra124) which runs the bootblock on a different architecture.
With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock.
Then, the bootblock loads the romstage over the verstage and exits to the
romstage. this is probably necessary for some SOC (e.g. rockchip) which does not
have SRAM big enough to fit the verstage and the romstage at the same time.
BUG=none
TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544
Reviewed-on: https://chromium-review.googlesource.com/212365
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds code to read the board ID from Pinky and put it into the
coreboot table.
(Note: This implementation differs slightly from Tegra since it pinmuxes
the GPIOs inside board_id(). That means the pinmuxing might be set more
than once if called in multiple stages, which is perfectly harmless and
in my opinion cleaner than having to (remember to) do it manually in one
of the per-stage files.)
BUG=chrome-os-partner:30167
TEST=With depthcharge patch, select -rev1 device tree for board ID 0.
Change-Id: I5b5689373e1e47b1e0944b5fe5f2e70a285b931f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217675
Reviewed-by: David Hendricks <dhendrix@chromium.org>
We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217674
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Some files for the veyron project were checked in with execute
permissions where it doesn't make sense. Fix.
BUG=chrome-os-partner:30167
TEST=None
Change-Id: Ia3788abf3755baf028518efb975701cf6cb37e46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217673
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The actual level required to take the ethernet switch out of reset is
low, not high.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217416
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The ALC283 needs a double function reset to ensure that all settings
are reset and the firmware beep is functional.
This is based on dlaurie's change from:
https://chromium-review.googlesource.com/#/c/167651/
BUG=chrome-os-partner:31824
BRANCH=None
TEST=build, boot, beep
Change-Id: I9109b598234ceaea365591468dd6766b89eb3cf0
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217127
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Mark GPIO42 as unused according to Samus schematics
BUG=None
TEST=Make the chnage; Pass the build process; Need someone having
the board perform the verification.
Change-Id: Ifd6a0d2de8af0fe3af4a14f44ce572b41b77509c
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/217344
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet
switch reset pit. The output stays low (or high-z) after power up,
which holds the switch in reset. Deassert the signal at startup on
hardware rev 1 and later.
BUG=chrome-os-partner:31780
TEST=with this patch applied, when proto0.2 boots, the ethernet
switch's LED blink once, as was the case with proto0.
Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217087
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config
Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Figuring out board_id on storm requires reading tertiary gpios, which
takes time. Let's calculate it once and reuse it when necessary.
BUG=none
TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2
respectively.
Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217086
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Now that arm64 and tegra132 has cpu devicetree support stop
using the bring_up_secondary_cpu option.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and brought up 2nd core.
Change-Id: I210bea73f8249de15f99d0c062600e789184eefd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216928
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216426
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31812
TEST=check if TS is found by the kernel
Change-Id: I22e6a9b65253bd17b639ce4d0742d1e7d3109e0c
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216527
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This function is breaking display bring up in the kernel. While
this functionality may be needed it's not until there is a
necessity to beep and/or bring up the display in firmware.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Sean ran with this patch and the display indeed did come up.
Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/216421
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I805d93e94f73418099f47d235ca920a91b4b2bfb
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209469
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
These are used by the LPDDR3 code in sdram.c.
Based on the schematic and email, I've filled in 4 slots
in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits
1:0) for Samsung SDRAM. I haven't tested the other 2 types of
RAM (Hynix and Micron). The 4th slot is a fallback slow Micron
config.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/216000
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are not needed/were never really used. SDRAM init will now
be done in sdram.c, not the BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built rush_ryu AOK.
Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/215863
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not much is happening yet, when the board is enabled (in the next
patch), all three components build successfully, the map files show
them placed where expected and the bopotblock is wrappeed in a BIMG
header.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214600
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add basic board support for the ImgTec Danube Virtual Platform, which
emulates a system built around the Danube SoC.
Run this by loading coreboot.bimg into a flash device connected to SPFI1
chip select 0 & then executing the Danube boot ROM.
BUG=chrome-os-partner:31438
TEST=none yet
Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The power button signal is driven from the silego part.
It's active high when the button is pressed.
BUG=None
BRANCH=None
TEST=Booted with power button pressed. vboot saw the press and
requested a shut down.
Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214847
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
