Add ddr3-samsung-2GB config and modify 533mhz linit.
Support ddr3 freq up to 800mhz.
Enable ODT at LPDDR3.
BUG=None
TEST=Boot Veyron Pinky
Change-Id: Ic02a381985796a00644c5c681b96f10ad1558936
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/220113
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Lin Huang <hl@rock-chips.com>
Commit-Queue: Julius Werner <jwerner@chromium.org>
This gives the EC some time to wake-up between asserting /CS and
starting a transfer.
BUG=chrome-os-partner:32223
BRANCH=none
TEST=verified ~100us delay using logic analyzer on Pinky
Change-Id: I9874e65abd405874c43c594d8caeeff9e1300455
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220243
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Commit-Queue: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Some ECs may require a few microseconds to ramp up their clock after
being awaken by /CS assertion. This adds a Kconfig variable that can
be overridden at the mainboard-level which will force a delay between
asserting /CS and beginning a transfer.
BUG=chrome-os-partner:32223
BRANCH=none
TEST=verified ~100us delay using logic analyzer
Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220242
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
This patch adds support for the board changes in rev2 (board_id = 0001).
It also moves the existing mainboard.c code around a bit to group it by
component.
BUG=chrome-os-partner:32139
TEST=Booted on rev1. Confirmed SD card still works. Confirmed power
button was still as broken as before.
Change-Id: Ifc4876687db64ca50e41d009d911446129d57b1b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220251
The static gpio_t initializers are stylish, but they are still a little
too annoying to write and read in day-to-day use. Let's wrap that in a
macro to make it a little easier to handle.
BUG=None
TEST=None
Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220250
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This updates timer.h to #include the header necessary for u32,
and to change the one instance of uint32_t to u32 to be uniform.
BUG=none
BRANCH=none
TEST=compiled
Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220612
Reviewed-by: Julius Werner <jwerner@chromium.org>
this change makes coreboot initialize kernel space and backup space in the tpm
when no firmware space is found in the tpm.
BUG=chrome-os-partner:32410
TEST=Forced factory initialization and verified it went through without errors.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I777e3cb7004870c769163827543c83665d3732b9
Reviewed-on: https://chromium-review.googlesource.com/220412
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
The Serial Peripheral Flash Interface (SPFI) block allows
communication with various devices over the SPI bus.
It uses a configurable transaction interface and it clocks
the bus according to the configured command, address, gap (aka
dummy) and data lengths.
This controller requires the SPI_ATOMIC_SEQUENCING flag set
(write and read done in the same transaction) as it cannot
directly control CS and will assert/de-assert CS at the
beginning/end of a transaction itself.
Note that the size of any transfer cannot be greater than
64KB - 1, as this is configured in a 16-bit field.
The SOC has 2 SPFI interfaces each of them providing 5 slave select
lines. SPFI 0 supports single and dual modes, SPFI 1 supports
single, dual and quad modes.
For SPFI interface 0:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi0clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set
- CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration paramters are also required:
Signal name Pad name MFIO mode
spim0_d0_txd MFIO_MIPS_10 0
spim0_d1_rxd MFIO_MIPS_9 0
spim0_mclk MFIO_MIPS_8 0
spim0_cs0 MFIO_MIPS_2 1
spim0_cs1 MFIO_MIPS_1 1
spim0_cs2 MFIO_MIPS_55 1
MFIO_MIPS_28 1
spim0_cs3 MFIO_MIPS_56 1
MFIO_MIPS_29 1
spim0_cs4 MFIO_MIPS_57 1
MFIO_MIMPS_30 1
For SPFI interface 1:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi1clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set
- CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration paramters are also required:
Signal name Pad name MFIO mode
spim1_d0_txd MFIO_MIPS_5 0
spim1_d1_rxd MFIO_MIPS_4 0
spim1_mclk MFIO_MIPS_3 0
spim1_d2 MFIO_MIPS_6 0
spim1_d3 MFIO_MIPS_7 0
spim1_cs0 MFIO_MIPS_0 0
spim1_cs1 MFIO_MIPS_1 0
MFIO_MIPS_58 1
spim1_cs2 MFIO_MIPS_2 0
MFIO_MIPS_55 2
MFIO_MIPS_31 1
spim1_cs3 MFIO_MIPS_56 2
spim1_cs4 MFIO_MIPS_57 2
BUG=chrome-os-partner:31438, chrome-os-partner:32441
TEST=Tested as bare-metal driver on Pistachio FPGA
Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://chromium-review.googlesource.com/217320
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This adds a mainboard-specific bootblock function that will be used
to set up some board-specific parameters which are currently set up
in the SoC bootblock function.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ibee7076ebd6080f04b0697067e85ce8b6b2230e4
Reviewed-on: https://chromium-review.googlesource.com/220399
Reviewed-by: Julius Werner <jwerner@chromium.org>
Danube has become Pistachio, let's rename all instances where this SOC
is mentioned.
BUG=none
TEST=board urara still builds
Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220401
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
The codec interrupt needs to come from codec GPIO1, so use the
HOTWORD_DET GPIO as the codec IRQ and the DSP_INT as the wake.The
This means codec interrupt is GPIO46 which is PIRQO and should be
interrupt 30.
Also add GPIO defines for the GPIOs attached to the codec itself.
These are defined by index, and I used the same "jack detect" and
"mic present" indices that were used in baytrail.
The codec interrupt to the host is added at index 2 and the
hostword detect interrupt to the host is added at index 3.
These can be changed as we work through the implementation in the
kernel driver.
BUG=chrome-os-partner:29649
BRANCH=samus
TEST=build and boot on samus
Change-Id: I1c1ac1b6095fab7e3f4412555db4f9a9138e528b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220326
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Actual timer support is not yet available for Danube, it will be added
soon. For now, just to make the target build, modify it to use
GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option.
BUG=none
TEST=the target builds again
Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220395
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC behavior for reading events from the ACPI interface was broken
with this commit:
d899fda lpc: ACPI query-next-event drops masked events
https://chromium-review.googlesource.com/194935
This is causing no EC wake events to be logged. To make sure they are
logged once again set the wake mask before querying for events.
Also remove the check for port80 event logging since this is no longer
used as we now store the port80 code in CMOS and this is unnecessary
commands to do for the resume path.
BUG=chrome-os-partner:32462
BRANCH=samus,auron
TEST=build and boot on samus, check for EC wake events for keyboard
and lid in the event log.
Change-Id: Icdd0c1a37a94e0cbd9fd256172324bf989e6d0dc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220373
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move _PRW to the ACPI devices for the touchpad and touchscreen.
Add a _DSW method, but disable it by default for now until a
spurious wake issue can be resolved.
BUG=chrome-os-partner:32232
BRANCH=samus
TEST=build and boot on samus, ensure trackpad does not
spuriously wake the system.
Change-Id: Ic4763f2cb5f3a59d04b236cee94906025661c615
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220325
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to report the GPE that woke the system to the kernel
coreboot needs to keep track of the first GPE wake source and
save it in NVS so it can be returned in \_GPE._SWS method.
This is similar to the saving of PM1 status but needs to go
through all the GPE0_STS registers and check for enabled and
triggered events.
A bit of cleanup is done for areas that were touched:
- ramstage.c:s3_resume_prepare() was not indented with tabs
- platform.asl was not formatted correctly
BUG=chrome-os-partner:8127
BRANCH=samus,auron
TEST=manual:
- suspend/resume and wake from EC event like keyboard:
ACPI _SWS is PM1 Index -1 GPE Index 112 ("special" GPIO27)
- suspend/resume and wake from RTC event:
ACPI _SWS is PM1 Index 10 GPE Index -1 (RTC)
- suspend/resume and wake from power button:
ACPI _SWS is PM1 Index 8 GPE Index -1
- suspend/resume and wake from touchpad:
ACPI _SWS is PM1 Index -1 GPE Index 13
- suspend/resume and wake from WLAN:
ACPI _SWS is PM1 Index -1 GPE Index 10
Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add event log entry if GPIO27 is used to wake the system.
This GPIO is treated separately from other GPE and it is
one of the only events that can wake from Deep Sx.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=samus: suspend/resume and wake from keypress, check for
GPIO27 event in event log.
Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220323
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the new battery status event to the SCI list so the
host can get notified when battery charge status changes.
BUG=chrome-os-partner:32196
BRANCH=auron
TEST=emerge-auron coreboot
Change-Id: Icc6182e65eb3a1d37442d3c0de1555b9ac2a2765
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220322
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Define specific GPIOs in gpio.h instaed of smihandler.c
- Add battery status event to SCI list
- Remove old proto board version defines and SPD index usage
- Do not disable cmd_pwr training now that it works on EVT board
BUG=chrome-os-partner:32196,chrome-os-partner:29117
BRANCH=samus
TEST=build and boot on samus
Change-Id: I53cf8d80ed7f675c10fa04e8fe8b879a4af9b21f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220321
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new host event to send a notify(0x80) to the battery
when the EC indicates that battery status has changed.
The kernel has fixed the bug with _BIX method so it can
be enabled now.
BUG=chrome-os-partner:32196
BRANCH=samus
TEST=build and boot on samus
Change-Id: I0ebb17e5441e875875d98168ce3c31486d57330e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add GENERIC_UDELAY Kconfig option so that a generic
udelay() implementation is provided utilizing the
monotonic timer. That way each board/chipset doesn't
need to duplicate the same udelay(). Additionally,
assume that GENERIC_UDELAY implies init_timer()
is not required.
BUG=None
BRANCH=None
TEST=Built nyan, ryu, and rambi. May need help testing.
Change-Id: Idd26de19eefc91ee3b0ceddfb1bc2152e19fd8ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219719
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of open coding monotonic timer usage,
use the stopwatch API.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219716
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=None, but similar usage tested on tegra132.
Change-Id: Iff3293debc2f85553c9e9b765084e5c00720012c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219713
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of using rela_time use the stopwatch API as the
semantics fit perfectly with the expiration usage.
BUG=None
BRANCH=None
TEST=Built, but similar usage tested on tegra132.
Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219712
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
It causes fan top speed due to this bug + our board-specific workaround,
and causes invalid temperature sensor readings.
Therefore, re-configure the register "External Temperature Sensor Host
Control Register" to terminate processes when this issue happens.
BUG=chromium:402204
TEST=ran suspend_stress_test 500 times
Change-Id: I6e71b6a46a31b00e541c304f1ed58c1678c1d42e
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219445
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Instead of open coding the monotonic timers use the stopwatch
abstraction.
BUG=None
BRANCH=None
TEST=Booted and noted timings work as expected. Built with software_i2c
and no compilation failures.
Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219495
Reviewed-by: Julius Werner <jwerner@chromium.org>
Simplify the timed operations by using the stopwatch API.
BUG=None
BRANCH=None
TEST=Built and booted to kernel. Analyzed logs. Output as expected.
Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219494
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Most Baytrail based devices MMIO registers are reported in ACPI
space and the device's PCI config space is disabled. The PCI config
space is required for many "legacy" OSs that don't have the ACPI
driver loading mechanism. Depthcharge signals the legacy boot
path via the SMI 0xCC and the coreboot SMI handler can switch the
device specific registers to re-enable PCI config space.
BUG=chrome-os-partner:30836
BRANCH=None
TEST=Build and boot Rambi SeaBIOS.
Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/219801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Tested-by: Mike Loptien <mike.loptien@se-eng.com>
Simplify the SPI timeout by using the stopwatch.
BUG=None
BRANCH=None
TEST=Built nyan. Confirmed stopwatch works independently.
Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219493
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
There's a lot of places where expiration and running time are
open coded. Allow for those places to be simplified by adding
a stopwatch construct. The stopwatch can have an expiration or
just be used to accumulate time.
BUG=None
TEST=Built and verified API works as expected by using implementation.
Change-Id: I53604900fea7d46beeccc17f1dc7900d5f28518b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219492
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
OBFF: Disable it by clear bit fields in that W/O register.
RO: Enable Relaxed Ordering from each enabled Root Port.
Linker Arbiter: Set it to recommeded setting.
BUG=None
TEST=Build a image and check the setting are applied correctly on
Samub.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c
Reviewed-on: https://chromium-review.googlesource.com/219993
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
Extended PCIe Capability and Advanced Error Report locates at
offset 0x100 is W/O, and the subsequent write following the 1st
write to the register takes no effect.
BUG=chrome-os-partner:31424.
TEST=Build a image and check the programming value is correct on
Samus.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I0bed30f516ee0307b4a86cad2f669a18ff4994db
Reviewed-on: https://chromium-review.googlesource.com/219985
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Auron/Peppy use GPIO 12 and GPIO 25 as wake up pins. GPIO_OWN,
GPIO_ROUTE, GPnCONFIG registers are setup if _DSW methods
are available.
Example capture after GPIO 12 and 25 are enabled for wake up:
GPIO Registers: GPIO_OWN_0 3dfbea0f GPIO_ROUTE_0 00000000
GPIO Registers: GPnCONFIGA_12 4000000d GPnCONFIGB_12 00000000
GPIO Registers: GPnCONFIGA_25 4000000d GPnCONFIGB_25 00000000
As Duncan suggested, I moved _PRW and _DSW to respective trackpad
and touch screen devices, and wake up worked with latest Chrome
image R39.6301.
Trackpad wake up is automatically enabled after boot. But touch
screen wake up is not enabled by powerd on boot.
BUG=chrome-os-partner:32047
TEST=check if trackpad can wake up board
Change-Id: Idd1e93dee8678044a6756cf36e8fdf4d27cd9676
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219906
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Configure IOSF Port and Grant Count.
BUG=None
TEST=Build coreoot image and run on Samus to confirm the setting
is properly applied.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: If387a23749b6e9470c7e67286234e18ab3e423b3
Reviewed-on: https://chromium-review.googlesource.com/219523
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
BUG=chrome-os-partner:32015
BRANCH=None
TEST=successfully suspend/resume on Rush/Ryu
Signed-off-by: Yen Lin <yelin@nvidia.com>
Change-Id: I11cca0a8f5e7a36c1fff690c8070c74706348949
Reviewed-on: https://chromium-review.googlesource.com/214580
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Yen Lin <yelin@nvidia.com>
Tested-by: Yen Lin <yelin@nvidia.com>
Copied dlaurie's entry from Rambi board. On Auron/Peppy
board, IRQ is hooked to GPIO 51. Based on table 5-36, this
is PIRQT. Then based on table 5-12, this is IRQ #35.
Thanks to Duncan for the pointer!
BUG=chrome-os-partner:32237
TEST=check if ALS is found by the kernel
Change-Id: I97bd932b48a6512632ee747715926a5761a7aeca
Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/219631
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
this change makes the bootblock jump to the verstage when VBOOT2_VERIFY_FIRMWARE
is set.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I868b2c1888a55fd181e10856fd0f58d01086355c
Reviewed-on: https://chromium-review.googlesource.com/219626
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this change makes prevent execution from falling through to unverified
code when hard_reset is not implemented. it also includes a few touch-ups.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I9b02ab766172a62c98b434c29f310bc4a44f342d
Reviewed-on: https://chromium-review.googlesource.com/219625
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
There's no need to add DMA ranges for these boards as
that memory is allocated within dpethcharge now. Additionally,
the DRAM_DMA_* Kconfig options were removed resulting in 0
values.
BUG=None
TEST=Built rush and ryu.
BRANCH=None
Change-Id: I52bb8f760a56226c75611f7981570a44d56f242e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219710
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
With VPD blob of certain format, CBFS cache on storm proves to be not
large enough. This patch makes it bigger, it is still well above the
area preserved for the NSS.
BUG=chrome-os-partner:32152
TEST=the system now boots with the VPD it used to fail booting.
Change-Id: Ia88b598ad5e4b6adcbd87d865e43be57fbf0ea98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219572
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pass MAC addresses found in coreboot table into lib_sysinfo.
BUG=chrome-os-partner:32152
TEST=with all changes in place MAC addresses are properly inserted
into the kernel device tree.
Change-Id: I1d0bd437fb27fabd14b9ba1fb5415586cd8847bb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219444
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Chrome OS devices firmware usually includes an area called VPD (Vital
Product Data). VPD is a blob of a certain structure, in particular
containing freely defined variable size fields. A field is a tuple of
the field name and field contents.
MAC addresses of the interfaces are stored in VPD as well. Field names
are in the form of 'ethernet_macN', where N is the zero based
interface number.
This patch retrieves the MAC address(es) from the VPD and populates
them in the coreboot table so that they become available to the
bootloader.
BUG=chrome-os-partner:32152, chromium:417117
TEST=with this and other patches in place the storm device tree shows
up with MAC addresses properly initialized.
Change-Id: I12c0d15ca84f60e4824e1056c9be2e81a7ad8e73
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coreboot generic CBFS media API does not support
multiple media access instances, but it should.
With this fix the CBFS context (memory cache for
SPI accesses) is shared among all open media access
streams. A better memory management scheme might be
required, but for now this fix allows to support
booting deptcharge and accessing VPD through two
independent CBFS media streams.
BUG=chrome-os-partner:32152
TEST=no exception is thrown when the second stream
is opened
Change-Id: Ib9d9d1f5209c2e515a95d7acbf4a8ac1255d3f8a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219441
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Flashmap offset needs to be defined through
configuration option. This definition must match
the FMAP location defined the appropriate device
tree in the deptcharge repository.
BUG=chrome-os-partner:32152
TEST=attempts to look up VPD in flash map do not
fail anymore
Change-Id: I474f0c4854fc264bcae8eb27fbd43966a381aa91
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219440
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
