Add an I3C driver that allows to use the I3C HW from the OS.
It does:
- Power on/off the I3C HW
- Configures the IOMUX
Add the SoC specific AOAC devices and GPIO pins to reconfigure
the GPIO for I3C HW.
New log messages are seen in coreboot:
[DEBUG] MMIO: fedd2000 disabled
TEST: The I3C driver loads on amd/glinda using Ubuntu 25.04.
Change-Id: Ibca20e2a4f0cb0e6006cfa47fd4addbe27504645
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Replace individual stage-specific lines with all-$() for each file.
This simplifies the Makefile from 6 lines to 2 lines while maintaining
identical functionality.
The all-$() variable automatically includes the file in all build stages
(bootblock, verstage, romstage, postcar, ramstage, smm), which is
exactly what the original code was doing manually for each stage.
Change-Id: Ie89ba86a545c548fcc4ad0eb48a5cbb33733b541
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID=0x5140
- Removes src/soc/intel/pantherlake/spi.c
- Updates Makefile.mk to remove spi.c compilation
The common code uses SOC_GSPI_DEVFN(n) macro directly.
TEST=Panther Lake Fatcat OS boots properly
Change-Id: Id7462deeb80c1efe32accf0ab7fc9fa68494ddfd
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91328
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID=0x5140
- Removes src/soc/intel/meteorlake/spi.c
- Updates Makefile.mk to remove spi.c compilation
The common code uses SOC_GSPI_DEVFN(n) macro directly.
Change-Id: I6ac7bdf4c9eeaab2d0d0ecbe8cd2ea2bf7f9ea19
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=4
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID=0x23a8
- Removes src/soc/intel/alderlake/spi.c
- Updates Makefile.mk to remove spi.c compilation
The common code uses SOC_GSPI_DEVFN(n) macro directly.
Change-Id: I346e6c6cbe95c8608009e5f9fc53dbcff5edba4e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91326
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN and
SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Adds CONFIG_SOC_INTEL_SPI_PSF_DESTINATION_ID (0x23b0 for PCH-H, 0x23a8
default)
- Removes src/soc/intel/tigerlake/spi.c
- Updates Makefile.mk to remove spi.c compilation
The common code uses SOC_GSPI_DEVFN(n) macro directly.
Change-Id: Ib195ffcc0d46f7e95eba2d0a2c66fbcdcca615a2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Switch to the common SPI device function driver implementation. This
eliminates platform-specific SPI code by leveraging the common driver
with platform-specific Kconfig and macros.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE_SPI_DEVFN in Kconfig
- Adds CONFIG_SOC_INTEL_SPI_DEV_MAX=3
- Removes src/soc/intel/jasperlake/spi.c
- Updates Makefile.mk to remove spi.c compilation
Note: This platform does not use PSF destination ID.
The common code uses SOC_GSPI_DEVFN(n) macro directly.
Change-Id: If42aa1f955bc0aae2698aac35dbe23b79c68bf09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91324
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a common driver for SPI device function to bus mapping. This
eliminates code duplication across Intel SoC platforms by providing
a generic implementation that can be configured via platform-specific
macros.
The driver provides:
- spi_soc_devfn_to_bus(): Convert device function to bus number using
platform-defined SOC_SPI_DEVFN(n) macros
- soc_get_spi_psf_destination_id(): Optional PSF destination ID support
for platforms that need it
Platforms must define SOC_SPI_DEVFN(n) in soc/pci_devs.h.
Platforms must define the following Kconfig:
- SOC_INTEL_SPI_DEV_MAX: Number of SPI controllers available on the
platform.
- SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF: To enable PSF designation, the
ID must be provided with SOC_INTEL_SPI_PSF_DESTINATION_ID.
- SOC_INTEL_SPI_PSF_DESTINATION_ID: (optional) PSF destination ID for
SPI controller.
Change-Id: I07ded6e6d2156a02eef7b4fea86ac1c8fa5ff3ce
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a common implementation of gspi_soc_bus_to_devfn() to reduce code
duplication across multiple Intel SoC platforms. This implementation
uses the SOC_GSPI_DEVFN(n) macro which must be defined by each platform
in their soc/pci_devs.h header to map GSPI bus numbers to PCI device and
function values.
This change enables consolidation of nearly identical gspi.c files from
Alder Lake, Meteor Lake, Panther Lake, Tiger Lake, Jasper Lake, Elkhart
Lake, Cannon Lake, and Skylake platforms.
The implementation leverages the existing
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX Kconfig option and includes
compile-time assertions to ensure the configuration is within supported
limits (up to 7 GSPI controllers).
Change-Id: I776cebd70968fd4b8bbab176bca0a446a0cc76ab
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91322
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Declaring named objects for constants is not ideal, especially when done
inside of a method (it is highly inefficient). Instead, use preprocessor
defines.
Change-Id: I2d9d17b820ee72ba628b44ae508a7c467c023dd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Introduce a common implementation for I2C device function to bus
number mapping that can be shared across multiple Intel SoC platforms.
The implementation uses:
- CONFIG_SOC_INTEL_I2C_DEV_MAX: Kconfig value for max I2C controllers
- SOC_I2C_DEVFN(n): SoC-specific macro for I2C devfn names
This eliminates duplicate code across platforms that follow the
standard I2C controller numbering scheme.
Change-Id: Ib242d7a839ccb26394794382098cecb658adf698
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91258
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 339ef9b5c9 ("soc/intel/common/block/lpc: Improve automatic
window opening") introduced a bug in the decoding of existing LPC I/O
window sizes from the LGIR (LPC Generic I/O Range) registers.
The AMASK field in the LGIR register stores bits [7:2] of the address
mask, with bits [1:0] implicitly always set to 1 (representing 4-byte
granularity). The original implementation incorrectly calculated the
window size as:
exist_size = 1 + ((reg32 & LPC_LGIR_AMASK_MASK) >> 16)
This fails to restore the implicit lower bits [1:0] of the mask.
For example, a window programmed with size 8 bytes:
- Stored mask: (8-1) & 0xfc = 0x4 (bits [7:2] only)
- Incorrectly decoded: 0x4 + 1 = 5 bytes (WRONG)
- Correctly decoded: (0x4 | 0x3) + 1 = 8 bytes (CORRECT)
This bug caused failures on Panther Lake boards where existing windows
were not recognized as covering requested ranges, leading to:
[ERROR] LPC: Cannot open IO window: 800 size 8
[ERROR] No more IO windows
The fix properly reconstructs the full mask by OR-ing in the implicit
bits [1:0] before calculating the size:
exist_size = ((amask_raw & 0xfc) | 0x3) + 1
BUG=b:486133237
TEST=Boot Panther Lake Fatcat board, verify no LPC window errors
Change-Id: I0b5f95c01da6ce84924a038106edec600e3b97f8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91418
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Migrate the low-battery power-off sequence in Intel common reset
logic to use platform_handle_emergency_low_battery().
This ensures that all Intel-based boards benefit from the unified
ChromeOS battery alert flow (LED notification and ELOG recording)
without duplicating the logic in the SOC layer.
BUG=none
BRANCH=none
TEST=Verified that low-battery shutdown on Intel platforms still
correctly logs ELOG and triggers visual alerts via the new hook.
Change-Id: I37c15a1f7dd5acee10389c0521e8c9b2f2d90d42
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Creation of named objects within a method is highly inefficient, as per
IASL's remarks during DSDT compilation. But it is possible to use local
variables instead of named objects to store a package.
Update the `GPLD` method to use a local variable, instead of creating a
named object. While at it, unify cosmetics of the several copies of the
method across the codebase.
TEST: Build coreboot for the ASRock Z97 Extreme6 (Lynx Point) and run:
- acpiexec -b "Evaluate _SB.PCI0.XHCI.HUB7.GPLD 0" build/dsdt.aml
- acpiexec -b "Evaluate _SB.PCI0.XHCI.HUB7.GPLD 1" build/dsdt.aml
Observe return value is the same before and after this change.
Change-Id: Id66322150c90309f42f574584728c6b1db353c0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91390
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates 12 lines of duplicate code.
The Skylake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_DEVFN_UARTn macros defined in
pci_devs.h.
This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: Id686de6bb4dd9ccf78644817881b2abfb5ae0352
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.
The cannonlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macro defined in
pci_devs.h.
This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: I819dc9853b4b44eb97238c1d5ad464dd9ccf7f9a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91248
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.
The elkhartlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macro defined in
pci_devs.h.
This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: I778faf19128f41509f70d324dd9ccf71d93cab0b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.
The jasperlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macro defined in
pci_devs.h.
This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: I8f7c68c8c44dd9ccf7cb49af8a3561a47d4aacc2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.
The tigerlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macros defined in
pci_devs.h.
This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: I9520bd3f4dd9ccf777e34c79a8c8237adb8b0fed
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91245
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.
The meteorlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the SOC_UART_DEVFN(n) macro defined in
pci_devs.h which uses token concatenation to map to platform-specific
PCI_DEVFN_UARTn definitions.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: Ic791eaa2521a44aba330e149fb0185094dd9ccf7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91243
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the defines for PCI register SMM_FEATURE_CONTROL to the header
soc/pci_devs.h like it's done on other server platforms as well.
While on it add BIT1 that will be used in the following commit.
TEST=Not a function change, thus untested.
Change-Id: Ib05bb129f069ab1a6f4752a2dac829b3b7b41ec9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Use existing define for SMRR and PMRR support instead of redefining
it in various places.
TEST=No functional change, thus untested.
Change-Id: Ie366a9d695800acd9713bd4e8393201a1f0a5ab2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91015
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the logo_bottom_margin from 100 to 200 in the display_logo
configuration if FRAMEBUFFER_SPLASH_TEXT Kconfig is enabled.
This adjustment ensures the OEM footer logo and associated
splash text are rendered higher on the screen, improving visibility
and alignment with updated UX requirements.
BUG=None
TEST=Boot MediaTek device and verify the splash text is 200px from
the screen bottom edge as expected.
Change-Id: I490e50e200dfffedf24cb30fe0ca6ea6ae037d3d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91383
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.
The pantherlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFN macro defined in
pci_devs.h.
This commit:
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: I59443ece21bc45c8b6986fdd2bc24dd9ccf7a543
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91244
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates 18 lines of duplicate code.
The Alder Lake uart.c simply defined uart_devices[] array with
PCH_DEVFN_UART* macros. The common driver now handles this using the
PCI_UART_DEVFNn macro defined in pci_devs.h.
This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk
Change-Id: Iafd4881c44dd9ccf7e204378bbafafbd1c884db0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91242
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces a common UART device list implementation that
eliminates duplication across multiple Intel SoC platforms. Instead of
maintaining nearly identical uart.c files in each platform directory,
this common driver uses platform-specific macros to define UART device
function numbers.
The common implementation expects each platform to define the following
macros in their soc/pci_devs.h header:
- PCI_DEVFN_UART0
- PCI_DEVFN_UART1
- PCI_DEVFN_UART2
This approach maintains platform flexibility while reducing code
duplication and simplifying maintenance. The driver is compiled across
all stages (bootblock, verstage, romstage, postcar, ramstage, smm) to
support various UART usage scenarios.
Change-Id: Iba82a2fe24dd9ccf704e4a0fadc481b63662b94d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91241
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Introduce a new directory structure src/soc/intel/common/feature/ for
sharing SoC-specific code across Intel SoC generations to reduce code
duplication.
Unlike the common block code (src/soc/intel/common/block/) which is
intended for reusable IP blocks, the feature code is for SoC-specific
functionality that is similar (but not identical) across multiple
generations. Platform-specific differences are handled through
configuration options or platform-specific macros.
This commit:
- Creates src/soc/intel/common/feature/ directory
- Adds feature/Kconfig defining SOC_INTEL_COMMON_FEATURE
- Adds feature/Makefile.mk to build subdirectories
- Updates src/soc/intel/common/Kconfig.common to source feature/Kconfig
- Updates src/soc/intel/common/Makefile.mk to include feature/ subdirs
- Documents the common code directory structure in
Documentation/soc/intel/code_development_model/code_development_model.md
Change-Id: Idb842376a0a785a6439eeeb5a3a934d0bc575b09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91360
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
In this case, the callback function already treated the option as if
it were a boolean option, which likely only worked by chance.
Change-Id: Ic4b86c45e4837fcdb30cf594bb7e30400864e77e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91356
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I6c4e44507fc371fc8b693b2289c58eb61ac84aa8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91355
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I3ac872881627179cb4ef344132bb601c78ca3a01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I7f3bb4f13a143e37869c22d66a514581a88deeb2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91353
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: If9030e770a59d9de87f7b0f2112887db6126aacf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91352
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I4e4f5c071f4299876e4ecd9defe7782c85eac3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91351
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Boolean options are intended to represent generic "Enable"/"Disable"
options, but without enum options' extra bloat in the CFR structures.
Change-Id: I4be1ac4644c461fd64766e27383e479ff518a889
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91350
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
