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cpu/intel: Use existing defines for MTRR_CAP_MSR

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Use existing define for SMRR and PMRR support instead of redefining
it in various places.

TEST=No functional change, thus untested.

Change-Id: Ie366a9d695800acd9713bd4e8393201a1f0a5ab2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91015
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2026-01-30 15:26:51 +01:00 • committed by Matt DeVillier
commit dfcd63370d
6 changed files with 5 additions and 15 deletions
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4
src/cpu/intel/haswell/haswell.h
View file

@ -103,10 +103,6 @@
#define SMBASE_MSR 0xc20
#define IEDBASE_MSR 0xc22
/* MTRR_CAP_MSR bit definitions */
#define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12)
/* Intel suggested latency times in units of 1024ns. */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73

4
src/cpu/intel/haswell/smmrelocate.c
View file

@ -124,10 +124,10 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
/* Write PRMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
if (mtrr_cap.lo & MTRR_CAP_SMRR)
write_smrr(relo_params);
if (mtrr_cap.lo & PRMRR_SUPPORTED) {
if (mtrr_cap.lo & MTRR_CAP_PRMRR) {
write_prmrr(relo_params);
/* UNCORE_PRMRR msrs are package level. Therefore, only
* configure these MSRs on the BSP. */

4
src/cpu/intel/model_1067x/mp_init.c
View file

@ -43,12 +43,10 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
#define SMRR_SUPPORTED (1 << 11)
static void per_cpu_smm_trigger(void)
{
msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED) {
if (mtrr_cap.lo & MTRR_CAP_SMRR) {
set_feature_ctrl_vmx();
msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
/* We don't care if the lock is already setting

4
src/cpu/intel/smm/gen1/smmrelocate.c
View file

@ -17,8 +17,6 @@
#include <console/console.h>
#include <smp/node.h>
#define SMRR_SUPPORTED (1 << 11)
#define D_OPEN (1 << 6)
#define D_CLS (1 << 5)
#define D_LCK (1 << 4)
@ -180,7 +178,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
/* Write EMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (!(mtrr_cap.lo & SMRR_SUPPORTED))
if (!(mtrr_cap.lo & MTRR_CAP_SMRR))
return;
if (cpu_has_alternative_smrr())

2
src/soc/intel/common/block/cpu/smmrelocate.c
View file

@ -164,7 +164,7 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
relo_params->smrr_mask.lo |= SMRR_PHYS_MASK_LOCK;
/* Write SMRRs if supported */
if (mtrr_cap.lo & SMRR_SUPPORTED)
if (mtrr_cap.lo & MTRR_CAP_SMRR)
write_smrr(relo_params);
}

2
src/soc/intel/common/block/include/intelblocks/msr.h
View file

@ -110,8 +110,6 @@
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg)
/* MTRR_CAP_MSR bits */
#define SMRR_SUPPORTED (1<<11)
#define PRMRR_SUPPORTED (1<<12)
#define SMRR_LOCK_SUPPORTED (1<<14)
#define SGX_SUPPORTED (1<<2)