soc/intel/cannonlake: Use common GSPI devfn mapping

Replace platform-specific gspi.c with the common GSPI device function
mapping implementation.

Changes:
- Select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN in Kconfig
- Define SOC_GSPI_DEVFN(n) macro in pci_devs.h
- Remove platform-specific gspi.c file

Change-Id: Ia6b7c8d9e0f1a2b3c4d5e6f7a8b9c0d1e2f3a4b5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91320
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/Kconfig

@@ -60,6 +60,7 @@ config SOC_INTEL_CANNONLAKE_BASE
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_FEATURE
+	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_I2C_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
 	select SOC_INTEL_COMMON_FSP_RESET

src/soc/intel/cannonlake/Makefile.mk

@@ -10,13 +10,11 @@ bootblock-y += bootblock/bootblock.c
 bootblock-y += bootblock/pch.c
 bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c
-bootblock-y += gspi.c
 bootblock-y += spi.c
 bootblock-y += lpc.c
 bootblock-y += p2sb.c
 
 romstage-y += cnl_memcfg_init.c
-romstage-y += gspi.c
 romstage-y += lpc.c
 romstage-y += pcie_rp.c
 romstage-y += pmutil.c
@@ -30,7 +28,6 @@ ramstage-y += elog.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += graphics.c
-ramstage-y += gspi.c
 ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += nhlt.c
@@ -52,10 +49,8 @@ smm-y += smihandler.c
 smm-y += xhci.c
 
 postcar-y += pmutil.c
-postcar-y += gspi.c
 postcar-y += spi.c
 
-verstage-y += gspi.c
 verstage-y += pmutil.c
 verstage-y += spi.c
 

src/soc/intel/cannonlake/gspi.c

@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gspi.h>
-#include <soc/pci_devs.h>
-
-int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
-{
-	switch (gspi_bus) {
-	case 0:
-		return PCH_DEVFN_GSPI0;
-	case 1:
-		return PCH_DEVFN_GSPI1;
-	case 2:
-		return PCH_DEVFN_GSPI2;
-	}
-	return -1;
-}

src/soc/intel/cannonlake/include/soc/pci_devs.h

@@ -208,6 +208,7 @@
 #define PCI_DEVFN_UART0		PCH_DEVFN_UART0
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
+#define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
 
 #endif