soc/intel/cannonlake: Use common UART device list driver

Remove platform-specific uart.c and switch to the common UART device
list driver. This eliminates duplicate code.

The cannonlake uart.c simply defined uart_devices[] array. The common
driver now handles this using the PCI_UART_DEVFNn macro defined in
pci_devs.h.

This commit:
- Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming
  consistency with common code
- Selects SOC_INTEL_COMMON_FEATURE and
  SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig
- Removes uart.c and updates Makefile.mk

Change-Id: I819dc9853b4b44eb97238c1d5ad464dd9ccf7f9a
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91248
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2026-02-19 07:43:36 -08:00 committed by Jérémy Compostella
commit a69d537e61
4 changed files with 7 additions and 18 deletions

View file

@ -59,6 +59,8 @@ config SOC_INTEL_CANNONLAKE_BASE
select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FEATURE
select SOC_INTEL_COMMON_FEATURE_UART_DEVICES
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_PCH_CLIENT

View file

@ -15,7 +15,6 @@ bootblock-y += i2c.c
bootblock-y += spi.c
bootblock-y += lpc.c
bootblock-y += p2sb.c
bootblock-y += uart.c
romstage-y += cnl_memcfg_init.c
romstage-y += gspi.c
@ -25,7 +24,6 @@ romstage-y += pcie_rp.c
romstage-y += pmutil.c
romstage-y += reset.c
romstage-y += spi.c
romstage-y += uart.c
ramstage-y += acpi.c
ramstage-y += chip.c
@ -46,7 +44,6 @@ ramstage-y += pmutil.c
ramstage-y += reset.c
ramstage-y += spi.c
ramstage-y += systemagent.c
ramstage-y += uart.c
ramstage-y += vr_config.c
ramstage-y += sd.c
ramstage-y += xhci.c
@ -55,20 +52,17 @@ smm-y += elog.c
smm-y += p2sb.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += uart.c
smm-y += xhci.c
postcar-y += pmutil.c
postcar-y += i2c.c
postcar-y += gspi.c
postcar-y += spi.c
postcar-y += uart.c
verstage-y += gspi.c
verstage-y += i2c.c
verstage-y += pmutil.c
verstage-y += spi.c
verstage-y += uart.c
ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
bootblock-y += gpio_cnp_h.c

View file

@ -204,4 +204,9 @@
#define PCH_DEV_GBE _PCH_DEV(LPC, 6)
#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7)
/* for common code */
#define PCI_DEVFN_UART0 PCH_DEVFN_UART0
#define PCI_DEVFN_UART1 PCH_DEVFN_UART1
#define PCI_DEVFN_UART2 PCH_DEVFN_UART2
#endif

View file

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <commonlib/helpers.h>
#include <soc/pci_devs.h>
const unsigned int uart_devices[] = {
PCH_DEVFN_UART0,
PCH_DEVFN_UART1,
PCH_DEVFN_UART2,
};
const int uart_devices_size = ARRAY_SIZE(uart_devices);