The romstage_main routine takes three parameters: bist, tsc_low and
tsc_hi. However in cache_as_ram.inc only the bist value is being
passed. This patch adds the two halves of the TSC value.
BRANCH=none
BUG=None
TEST=Build and run on Samus
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e
Reviewed-on: https://chromium-review.googlesource.com/231173
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The bootblock on Rush had bumped up into the verstage
allocation, causing the build to break. Reduced verstage from
60K to 58K and increased bootblock from 20K to 22K. Rush and
Ryu both build fine now.
BUG=none
BRANCH=none
TEST=Built both Rush and Ryu OK. Verifed verstage size
using cbfstool and it's around 55K, so plenty of room.
Change-Id: I7018f027d72d5e8aeb894857a5ac6a0bdc1de388
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/230824
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Secondary CPUs were intermittently not coming online as expected.
Upon investigation it was found that a cache line needed to be
invalidated that corresponded to the top of the stack for the
failing CPU.
Currently the secondary CPUs come online with caching disabled.
However, the code paths are using C and thus the stack it is assigned.
The MMU is enabled in C after it's pushed its return path onto the
stack that went directly to ram. When the cache line corresponding
to its stack is valid in the cache it will hit once the MMU is enabled.
That hit will have invalid data w.r.t. the return addresses pushed
directly into ram.
This is not the best solution as the only way to guarantee we don't
hit such a situation is to tightly manage resource usage up until
the point of MMU enablement. That can be done in a followup patch.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=On ryu where secondary CPUs weren't coming online consistently,
they now come up.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I32de749ea48c19e23442e6dc5678c5369ac3b2b6
Reviewed-on: https://chromium-review.googlesource.com/231219
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Implement VOP and eDP drivers, vop and edp clock configuration,
framebuffer allocation and display configuration logic.
The eDP driver reads panel EDID to determine panel dimensions
and the pixel clock used by the VOP.
The pixel clock is generating using the NPLL.
BUG=chrome-os-partner:31897
TEST=Booted Veyron Pinky and display normal
BRANCH=None
Change-Id: I61214f55e96bc1dcda9b0f700e5db11e49e5e533
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/219050
Reviewed-by: Julius Werner <jwerner@chromium.org>
Extend lib/reg_script.c to use a platform table to declare
additional platform specific register access routine functions.
REG_SCRIPT_TYPE_PLATFORM_BASE is the starting value for platform
specific register types. Additional register access types may be
defined above this value. The type and access routines are placed
into reg_script_type_table.
The Baytrail type value for IOSF was left the enumeration since it
was already defined and is being used for Braswell.
BRANCH=none
BUG=None
TEST=Use the following steps to test:
1. Build for a Baytrail platform
2. Build for the Samus platform
3. Add a platform_bus_table routine to a platform which returns the
address of an array of reg_script_bus_entry structures and the
number of entries in the array.
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/215645
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7cd37abc5a08cadb3166d4048f65b919b86ab5db
Reviewed-on: https://chromium-review.googlesource.com/229612
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Merge change from coreboot.org: Add new finalize functions for devices
and chips
BUG=None
TEST=Requires FSP for testing
commit 2a58ecde78
Author: Marc Jones <marc.jones@se-eng.com>
Date: Tue Oct 29 17:32:00 2013 -0600
Add new finalize functions for devices and chips
Many chipset devices require additional configuration after
device init. It is not uncommmon for a device early in the
devicetree list to need to change a setting after a device later
in the tree does PCI init. A final function call has been added
to device ops to handle this case. It is called prior to coreboot
table setup.
Another problem that is often seen is that the chipset or
mainboard need to do some final cleanup just before loading the
OS. The chip finalize has been added for this case. It is call
after all coreboot tables are setup and the payload is ready to
be called.
Similar functionality could be implemented with the hardwaremain
states, but those don't fit well in the device tree function
pointer structure and should be used sparingly.
Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f
Reviewed-on: http://review.coreboot.org/4012
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: I4f918a5908f2016f6e57f954284f9f8856bd8301
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/213694
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229572
Reviewed-by: Erik C Bjorge <erik.c.bjorge@intel.com>
The initial MP code assumed all CPUs would come online. That's not
very defensive, and it is a bad assumption. Provide a timeout
mechanism for bring CPUs online.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=Multiple times with CPUs working and not working. Boot to kernel.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifb3b72e3f122b79e9def554c037c9b3d6049a151
Reviewed-on: https://chromium-review.googlesource.com/231070
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add the common header files for FSP 1.1. The are provided in an
EDK2 style tree to allow direct comparison with the EDK2 tree.
BRANCH=none
BUG=None
TEST=Build with FSP
Change-Id: I6f7316c8a31ec75d3593c950fe227a776a3e18a5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/229618
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add the common header files for EDK2. These files come from the
open source EDK2 tree https://svn.code.sf.net/p/edk2/code/trunk/edk2
revision 16227. The are provided in an EDK2 style tree to allow
direct comparison with the EDK2 tree.
The following files were modified to remove trailing spaces and add
some #ifndef/#endif conditionals:
* MdePkg/Include/Base.h
* MdePkg/Include/Ia32/ProcessorBind.h
* MdePkg/Include/Uefi/UefiBaseType.h
* MdePkg/Include/X64/ProcessorBind.h
A patch for the files above has been submitted to
edk2-devel@lists.sourceforge.net for inclusion into a future revision
of EDK2's MdePkg.
Note: All the files below were modified to use Linux line termination.
BRANCH=none
BUG=None
TEST=Build with FSP
Change-Id: Icaeb0cde301c7d555e5d55a95932efc1bc315d40
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/229617
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add a new memory type for the next build, and rename the existing
ones to drop the Gb suffix.
BUG=chrome-os-partner:33924
BRANCH=samus
TEST=build and boot on samus
Change-Id: I47d2b7e58f51f3ee00cd7797da3f8353f509f8b5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230769
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently the rt5677 codec outputs 6MHz PDM clock which is
out-of-spec for the speaker amp SSM2537. The amp's GAIN_FS
pin is pulled down to PGND with a 47k resistor, so the
expected PDM clock is 64*FS (~3MHz) according to its datasheet.
The corresponding kernel patch that adds the PDM clock config
option is https://chromium-review.googlesource.com/#/c/230303/
BUG=chrome-os-partner:33303
BRANCH=samus
TEST=flash coreboot with this patch and see PDM CLK went
from 6MHz to 3MHz on samus with a scope.
Change-Id: I09acdf47bab4f641981491a84197de234918435e
Signed-off-by: Ben Zhang <benzh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230344
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The kernel does not correctly function without PLLD being enabled.
Additionally, PLLD can be the source for other clocks in the system.
Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT
time in ramstage.
BUG=chrome-os-partner:33825
BRANCH=None
TEST=Built and booted ryu with display coming up both in dev mode as
well as normal mode.
Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230774
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Sean Paul <seanpaul@chromium.org>
Provide an explicit name for configuring PLLD. The new name,
clock_configure_plld(), provides an explicit semantic to
what it is doing. Also, provide the printk() about actual
frequency vs requested frequency as most of the callers
were doing this themselves.
BUG=chrome-os-partner:33825
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: If744332b466d9486f83b08d0ab4e9006fadfecdd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230773
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
This was copied and pasted more than it should have been...
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I2af9a30f3df733af147e8759f78a9802d2296c0f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is the unified FSP interface code from coreboot.org. To present
a consistent interface with the FSPs for all of the different CPUs,
and to cut down on code maintenance, all of the FSPs use this
interface.
Bug=None
Test=Builds and runs on Broadwell
Change-Id: Idcca5c42b06c47c67946c706e424e0349405ddf0
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/221182
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/229573
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Ryu RT5677 audio codec uses EXTPERIPH1 clock (12MHz)
for MCLK1, I2S1 for input. AHUB needs all of its child
peripherals taken out of reset and enabled, too.
This just sets up the audio clocks. More work still to
be done in the codec driver, and some kind of stub needs
to be created/hacked to set up the AD4567 speaker amp
regs for mono output on P1.
BUG=chrome-os-partner:32582
BRANCH=none
TEST=Dumped clock regs and saw correct values
Change-Id: I6c9e760ac39def92a6054d673f781facdbfd70a2
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229993
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This value apparently changed to 0x27 in the hardware but was
never adjusted in firmware.
BUG=chrome-os-partner:33790
BRANCH=samus
TEST=build and boot on samus
Change-Id: I10ca7b77068491e143f8bf2463b481eada910618
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are board specific adjustments that can be made for each
USB3 port.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: Iab92ff7b0218d4abd9eba8a94d34ddd9a30ddb87
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230231
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PHYSICAL_REC_SWITCH is set n by default and y for panther and stumpy.
BUG=none
BRANCH=ToT
TEST=Built nyan_blaze using vboot1/2. Built falco, lumpy, nyan,
blaze, parrot, rambi, samus, storm, pinky with default configuration.
panther and stumpy are not tested because they currently don't build on ToT.
Change-Id: Ic45f78708aaa7e485d2ab459fd1948524edb412f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/227940
Reviewed-on: https://chromium-review.googlesource.com/229602
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This changes copies firmware version from vboot2 shared data to vboot1
shared data. This fixes FAFT firmware_TPMVersionCheck test.
BUG=none
BRANCH=ToT
TEST=firmware_TPMVersionCheck passed on Nyan Kitty.
Change-Id: Idfd282931421dc16cd1aa82c7ccb6c6790a4d0d7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230186
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Yen Lin <yelin@nvidia.com>
When displaying a 800x600 bitmap on 2560x1800 panel, the image
is shown very small. So, set the fb to 1280x800 (based on tegra
dsi driver default mode setting), a 800x600 image can be shown
relatively proportional to panel size.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: I62cbe9de1d1002293df20f8b1d752905c6ef33aa
Reviewed-on: https://chromium-review.googlesource.com/229912
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Framebuffer line size and number of lines can have different
values than panel's resolution.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Change-Id: Iedeef796f02286bb03920413420f8952cf34334a
Reviewed-on: https://chromium-review.googlesource.com/229915
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
panel spec such as resoultion, bits per pixel are
needed to pass to depthcharge/payload for displaying
bitmap onto panel.
BRANCH=none
BUG=chrome-os-partner:31936
TEST=build and test on ryu
Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/227203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This should allow the max98090 codec to play beeps via
AHUB/I2S1 thru the depthcharge sound driver.
BUG=none
BRANCH=none
TEST=Saw max98090 codec init signon and register dump.
No sound yet.
Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229496
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Mike Frysinger <vapier@chromium.org>
If all devices under AHUB (AUDIO/I2S/DAM/ADX/etc) aren't
clocked and taken out of reset, any access to any audio
peripheral will hang the system.
BUG=none
BRANCH=none
TEST=built both Rush and Ryu OK.
Change-Id: I741d5ba4dd8bd963b6d261fbf41cfb77c274cb79
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Mike Frysinger <vapier@chromium.org>
Some actions are needed and some are not on the way resume from S3.
BRANCH=master
BUG=chrome-os-partner:33025,chrome-os-partner:33796
TEST=Built the image and confimed the boot_mode is correctly
configured.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: Ia042ea8c63c2306e9d6a80d8efa66c4fc0722d85
Reviewed-on: https://chromium-review.googlesource.com/229615
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Tested-by: Kenji Chen <kenji.chen@intel.com>
I2C1 was missing in the funit/i2c/addressmap tables/code.
BUG=none
BRANCH=none
TEST=Built Rush and Ryu. Built Rush w/code in mainboard.c
to enable I2C1 for the MAX98090 audio codec - codec could be
read/written.
Change-Id: Ibe4f012fa2d427b95cd4672687132b47576b6a9a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/229574
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Like most newer Chromebooks, Pinky and Jerry do not have physical
dev switches.
BUG=chrome-os-partner:33395
BRANCH=none
TEST=built and booted on Pinky, crossystem prints a valid value for
devsw_cur instead of an error.
Change-Id: I186518a59699d293c7938221b3ae45b27361c255
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229680
Reviewed-by: Julius Werner <jwerner@chromium.org>
The TPS65913 PMIC has an RTC built into it. This change adds
a driver for it which implements the new RTC API.
BUG=chrome-os-partner:33764
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu. Timestamps for event log
verified across multiple boots.
Change-Id: If1d549ea2361d0de6be75fd24b9e9810a6df7457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/229414
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This patch adds support for Pinky rev3 (board ID 2) and Jerry rev2: the
power button GPIO changed polarity to low, the 5V_DRV pin for USB power
was moved to the AP again (welcome back!), and the EMMC_RST_L is now
finally on a port with the right IO voltage so we don't need any weird
pull-up tricks anymore. Since there are very few Jerry rev1s around,
we'll just move it over to the new code directly without introducing
board ID differences (also, because I have no idea how they stuffed it
this time... is this one actually called rev2?).
BRANCH=None
BUG=None
TEST=Still boots on my Pinky rev2, though that doesn't say much.
Change-Id: Iddee360fbda357ecde4ae5fbb5c3a01fe0c22474
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229010
Reviewed-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This patch ports commit 567f616f (rk3288: slowly raise to max cpu
voltage to prevent overshoot) to Veyron_Jerry. It also fixes include
ordering and some comment grammar in the affected code.
BRANCH=None
BUG=chrome-os-partner:32716
TEST=None
Change-Id: I9c0aba40ddd8a0852391df184034baa740d063df
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Stack and Timestamp need lesser than 2K and since romstage is running out of
memory, adjust the overall memory assignment.
BUG=chrome-os-partner:33676
BRANCH=None
TEST=Compiles and boots to kernel prompt.
Change-Id: I0134f25dd49f2940bb159d131aaee12f81e13ef7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/229001
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Commit-Queue: Tom Warren <twarren@nvidia.com>
spi_flash->write returns non-zero on error and zero on success, not the
number of bytes written.
BUG=none
BRANCH=ToT
TEST=Booted storm. Verified successfully nvdata was saved.
Change-Id: If50cc1a62a4f06398d1830cca60085b6f925fff3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229389
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Provide support for SoCs to participate in PSCI
commands. There are 2 steps to a command:
1. prepare() - look at request and adjust state accordingly
2. commit() - take action on the command
The prepare() function is called with psci locks held while
the commit() function is called with the locks dropped. For
now, the one SoC doesn't implement the appropriate logic
yet.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=Booted PSCI kernel -- no SMP because cmd_prepare()
knowingly fails. Spintable kernel still brings up both
CPUs.
Change-Id: I0821dc2ee8dc6bd1e8bc1c10f8b98b10e24fc97e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226485
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Newly turned on CPUs need a place to go bring its EL3
state inline with expectations. Plumb this path in for
CPUs turning on as well as waking up from a power down
state. Some of the infrastructure declarations were
moved around for easier consumption in ramstage and
secmon. Lastly, a psci_soc_init() is added to
inform the SoC of the CPU's entry point as well do
any initialization.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and booted. On entry point not actually utilized.
Change-Id: I7b8c8c828ffb73752ca3ac1117cd895a5aa275d8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228296
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
It can't compile due to tpmp flag was removed in nvs.h
BRANCH=none
BUG=none
TEST=compile ok and boot to OS on pearlvalley
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I718b70c6194365ee19b93224b52b7bcf3a5055d0
Reviewed-on: https://chromium-review.googlesource.com/228975
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Tested-by: Kane Chen <kane.chen@intel.com>
