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Lee Leahy 36eebadc67 FSP 1.1 Header Files 
Add the common header files for FSP 1.1.  The are provided in an
EDK2 style tree to allow direct comparison with the EDK2 tree.

BRANCH=none
BUG=None
TEST=Build with FSP

Change-Id: I6f7316c8a31ec75d3593c950fe227a776a3e18a5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/229618
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-11-20 20:49:26 +00:00
..
arch arm64: psci cmd support 2014-11-12 19:57:38 +00:00
console console: add configs to support Marvell bg4cd uart 2014-10-17 03:24:42 +00:00
cpu urara: Fix CBFS header definitions 2014-11-11 18:02:20 +00:00
device PCIe: Add L1 Sub-State support. 2014-10-10 04:36:50 +00:00
drivers broadwell_fsp: Add intel FSP "driver" from coreboot.org 2014-11-19 04:10:00 +00:00
ec chromeec: Add wakeup delay after SPI /CS assertion 2014-10-01 06:53:27 +00:00
include broadwell_fsp: Add intel FSP "driver" from coreboot.org 2014-11-19 04:10:00 +00:00
lib broadwell_fsp: Add intel FSP "driver" from coreboot.org 2014-11-19 04:10:00 +00:00
mainboard samus: Add new memory type 2014-11-19 23:17:49 +00:00
northbridge Makefile: Preprocess linker scripts and other general improvements 2014-10-02 07:02:10 +00:00
soc broadwell: Add microcode rev 0x16 2014-11-19 23:17:57 +00:00
southbridge timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS 2014-11-07 01:24:01 +00:00
superio superio: ite8772f: Exit extemp busy state 2014-09-27 07:09:25 +00:00
vendorcode FSP 1.1 Header Files 2014-11-20 20:49:26 +00:00
Kconfig cbtables: Add RAM config information 2014-11-11 21:45:59 +00:00