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Broadwell: Pass TSC value to romstage_main

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The romstage_main routine takes three parameters: bist, tsc_low and
tsc_hi.  However in cache_as_ram.inc only the bist value is being
passed.  This patch adds the two halves of the TSC value.

BRANCH=none
BUG=None
TEST=Build and run on Samus

Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e
Reviewed-on: https://chromium-review.googlesource.com/231173
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Lee Leahy 2014-11-20 16:56:44 -08:00 • committed by chrome-internal-fetch
commit de565f28dc
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/broadwell/romstage/cache_as_ram.inc
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@ -181,7 +181,13 @@ clear_mtrrs:
/* Restore the BIST result. */
movl %ebp, %eax
/* Build the call frame. */
movl %esp, %ebp
movd %mm1, %ebx
pushl %ebx
movd %mm0, %ebx
pushl %ebx
pushl %eax
before_romstage: