Lee Leahy de565f28dc Broadwell: Pass TSC value to romstage_main ... The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Reviewed-on: https://chromium-review.googlesource.com/231173 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2014-11-22 00:13:11 +00:00
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arch	arm64: ensure secondary CPU's stack tops are not in the cache	2014-11-21 12:12:13 +00:00
console	console: add configs to support Marvell bg4cd uart	2014-10-17 03:24:42 +00:00
cpu	urara: Fix CBFS header definitions	2014-11-11 18:02:20 +00:00
device	Broadwell FSP: Add new finalize functions for devices and chips	2014-11-20 20:49:36 +00:00
drivers	broadwell_fsp: Add intel FSP "driver" from coreboot.org	2014-11-19 04:10:00 +00:00
ec	chromeec: Add wakeup delay after SPI /CS assertion	2014-10-01 06:53:27 +00:00
include	Add table driven way to add platform specific reg_script routines	2014-11-20 23:04:25 +00:00
lib	Add table driven way to add platform specific reg_script routines	2014-11-20 23:04:25 +00:00
mainboard	veyron: Add veyron_mighty board	2014-11-21 06:23:28 +00:00
northbridge	Makefile: Preprocess linker scripts and other general improvements	2014-10-02 07:02:10 +00:00
soc	Broadwell: Pass TSC value to romstage_main	2014-11-22 00:13:11 +00:00
southbridge	timestamp: remove conditional #if CONFIG_COLLECT_TIMESTAMPS	2014-11-07 01:24:01 +00:00
superio	superio: ite8772f: Exit extemp busy state	2014-09-27 07:09:25 +00:00
vendorcode	FSP 1.1 Header Files	2014-11-20 20:49:26 +00:00
Kconfig	cbtables: Add RAM config information	2014-11-11 21:45:59 +00:00