Provide a common function to issue reboot commands to the EC.
Expose that function for external use and use it internal to
the module.
BUG=b:35580805
Change-Id: Ia0668359af2bb9acd0ad5c9086b63dcd3228e926
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e68d22fbbc
Original-Change-Id: I1458bd7119b0df626a043ff3806c15ffb5446c9a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19573
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498313
Use register name instead of hex values.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: If7cb7a02841f960f547eaba62f9455499f6ad593
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c368620d60
Original-Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19545
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498310
Use register name instead of hex value.
No functional change.
BUG=none
BRANCH=none
TEST=none
Change-Id: I3ed947b8d353083053e801d555239f2805bfe717
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c31af8e1a
Original-Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19544
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498309
This patch adds the eMMC as one of the thermal sensor under DPTF.
Also, updates few comments for better interpretation and mapping.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: I22edad5afd0e24fd19ee7857b750f0168d13a818
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c9026b2945
Original-Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19524
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498308
Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I4488a6d4abbf90f34e5f7174ab71a6e62c5cb996
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8caf8a23f9
Original-Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/19538
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/498307
The current implementation is incorrect and is
actually disabling the ports. Fixes that.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I908c1ab04b6d5fd823a89bf1a1eae3116920e468
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d44d028050
Original-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19553
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497404
Turn on device 1c.0 in order to enable devices
under it.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=Boot from NVMe
Change-Id: I87c1f0a96067ec92f3df623f5327be243d53171f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f49785e8e2
Original-Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19533
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497403
This is required to ensure that SCI is generated whenever a host event
is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs,
eSPI SCI is generated which results in kernel handler reading host
event from the EC and thus causes the wake pin to be de-asserted.
BUG=b:37223093
TEST=Verified that wake from mode change event works fine in suspend
mode and there is no interrupt storm for GPE SCI after resume.
Change-Id: Ib82e9291b55c68a4508bd1ce3f5f5ad08fdb228e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 730fc6c7d8
Original-Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19559
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/497399
soc/i2c.h does not need to be included in this compilation unit.
BUG=none
BRANCH=none
TEST=none
Change-Id: I57bb42eb4565e9bf2faf7bce34b1115524e913dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c2b1390d47
Original-Change-Id: Ife11642d2e69af7235c93fc54bba38853b046169
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19572
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/497398
According to Yang York the FSP is responsible for switching the CPU into
high frequency mode (HFM). For an unknown reason this is not done for the
BSP on my platform though the APs are switched properly.
This code switches the CPU into HFM which makes sure that all cores are in
high frequency mode before payload is started.
It should not harm the operation even if FSP was successful in switching
to HFM.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia2e05152d0bfa7280d039c66c18eb5e38763c082
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf6392f756
Original-Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Original-Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/19537
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/497397
Remove struct skylake_i2c_config from chip.h since it is not used
anymore.
BUG=none
BRANCH=none
TEST=none
Change-Id: I00e7670f3380e5ab23c5860ebe3fbde501d5bf65
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bfcc1e37b9
Original-Change-Id: Icde4b7af5b9c31020099c1a6372a6867827f61ae
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19520
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/497396
Currently native video init works on port HDMI1 (wired to the
on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA
port, both text mode and fb mode.
Every ports works on GNU/Linux.
Tested against an IVB cpu (i7-3770T).
BUG=none
BRANCH=none
TEST=none
Change-Id: I637c593db52f54f044eb644dea0054c406e17c0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91fbb25ec7
Original-Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Original-Signed-off-by: Bill XIE <persmule@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19522
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/497395
The checkreset() function checks if raminit previously
succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a
hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the
system BOOT_PATH_RESET path will be taken. This boot path can only
successfully initialize memory if the system was reset from a state
where raminit succeeded, which is not the case here.
This can be fixed by issuing a cold reset instead of a hot reset.
BUG=none
BRANCH=none
TEST=none
Change-Id: I4b9d826e63c89a67190c8acfe9ce8e459f77623e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8565c03caf
Original-Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19506
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/497394
device is run before drivers to generate .config and the first default
takes precedence so this override achieves nothing.
BUG=none
BRANCH=none
TEST=none
Change-Id: I275e68349ad606785b444ccbb2fcefd459749e93
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a93387b0d5
Original-Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19511
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496056
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
BUG=none
BRANCH=none
TEST=none
Change-Id: I6df100df0f80ce479ace6ee2c1d59114c17f1a7a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20cb85fa98
Original-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19500
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496055
This allows to use EDID data outside of NGI path without needing to
fetch it twice.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iae2da8ce54bcdbe4836a900bb0ef43b333366153
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 53485d2eab
Original-Change-Id: I6a540b1d036a9f38b44fd004309601630861f6e7
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19503
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/496053
Remove the code that was enabling the keyboard backlight at boot
since this is not desired behavior for this device.
BUG=b:35581264
TEST=build and boot on Eve and ensure keyboard backlight does
not turn on when booting but can still be enabled in the OS.
Change-Id: Ifd608411b96d39894bec44084803011d910b9543
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec10c9a11c
Original-Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19550
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/496050
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: I66e41615c4a19083b8bc5835f1139e8f15cd372b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1a51086815
Original-Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19549
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/496049
Commit-Ready: Duncan Laurie <dlaurie@google.com>
Kevin's center logic isn't super clean so it needs 925 mV for center
logic. All newer gru variants only need 900 mV.
BRANCH=gru
BUG=b:37429075
TEST=Reboot tests
Change-Id: I8c3bd6c245700b23c27cd5758c35c9993f801cb4
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/479463
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19357
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/480971
Reviewed-by: Julius Werner <jwerner@chromium.org>
Board Scarlet doesn't use usbphy1.
BUG=b:37685249
BRANCH=gru
TEST=boot Scarlet, check the firmware log, and confirm
no errors about USB1
Original-Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I3b62ea72c1db33fe8eb6386be38989f223d85039
Reviewed-on: https://chromium-review.googlesource.com/494906
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
1. Add support for using cr50 I2C TPM on poppy. This will not be
enabled until the next build.
2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding
Kconfig options are set.
BUG=b:36265511
TEST=Verified on a reworked board that I2C TPM communication works
fine.
Change-Id: I570504113c8da06d5834a3d80a10353d1e41fdfa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 553f7fb27c
Original-Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19518
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494608
When using Wake On Voice &/or DCI, it requires xtal to be active during
low power idle.
With xtal being active in S0ix state power impact is 1-2 mW.
Hence set xtal bypass bit in CIR31C for low power idle entry.
TEST= Build with s0ix enable for Poppy. Boot to OS & verify that
bit 22 of CIR31C register is set. s0ix works.
Change-Id: Iaffe8defdc559fad908b852903db06725c1bf005
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c261c4b426
Original-Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19442
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/494050
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Add a configuration option to assign the binaryPI base address
for the ACPI registers. The binaryPI's assignment is determine
at build time and no run-time configuration is allowed.
BUG=none
BRANCH=none
TEST=none
Change-Id: I2fa71ebe07b6d20e0d7bd9302a35c17b543c00ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7f2c29b6d6
Original-Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19485
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494049
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Claim memory-mapped regions in the legacy area.
Claim an MMIO resource for the A000 and B000 segments, and reserved
resource for C000 through F000 segments.
These changes allow code and information to be retained in the event
unused regions get wiped.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d612d4fe69881609d42053496409c452e1014947)
BUG=none
BRANCH=none
TEST=none
Change-Id: Ic5f61a63499db3b882f06ec4c8642519196d1a88
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a7ebd4e08
Original-Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/494048
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Define a common area in CAR so that the storage data structures can be
shared between stages.
TEST=Build and run on Reef
Change-Id: I300059af6ef55d777eb9606c88f0a7f91d024b0c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 43d0d0d1f4
Original-Change-Id: I20a01b850a31df9887a428bf07ca476c8410d33e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19300
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/494046
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Create Intel Common FAST_SPI Controller code.
This code contains the code for SPI initialization which has
the following programming -
* Get BIOS Rom Region Size
* Enable SPIBAR
* Disable the BIOS write protect so write commands are allowed
* Enable SPI Prefetching and Caching.
* SPI Controller register offsets in the common header fast_spi.h
* Implement FAST_SPI read, write, erase APIs.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ifd05fa75ddd34ae5df48e4dee0618f30b8d23654
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 89331cd4c8
Original-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18557
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493985
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: I4dee11445385e7c6189593d8a09558e5cd8b7bac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 281ccca373
Original-Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19310
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493984
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: I355d6a04d31cb42a6113e32429a82eea0f924d0b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2be2840a1d
Original-Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19309
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493983
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib359f8a42946da6a293b456ca087b899d53cf9cc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0eb6cd8bd
Original-Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19307
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493982
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
The AFCAdditional Flash Control Register is set by
southbridge code.
Remove redundant calls and get rid of it in autoport.
BUG=none
BRANCH=none
TEST=none
Change-Id: I912dc6f185b7df5e1b54aa90e64d7cfdb0bc0d63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0a4a4f7ae4
Original-Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19493
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/493981
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Based on Thinkpad x230 and schematics.
Verified by autoport.
USB debug port is the left front usb port
Thanks to Holger Levsen for the device.
BUG=none
BRANCH=none
TEST=none
Change-Id: Iec695049d8bf2e115011b513af3d4eebe5b433a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db508565d2
Original-Change-Id: I97c8e01a3ce0577d7dc9e8df7d33db3b155fe3d6
Original-Tested-on: lenovo x1 carbon gen 1
Original-Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Original-Reviewed-on: https://review.coreboot.org/16994
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/493980
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices'
FADT version were incorrectly set to 3, rather than the correct
ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these
devices reporting compliance to ACPI 2.0, rather than ACPI 3.0.
This mirrors similar recent changes to SKL and APL SoCs.
Test: boot any affected device and check ACPI version reported
vai FADT header using OS-appropriate tools.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ia974300bdc555a1062d2779083a19c3838f6cf78
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7ee81a4a01
Original-Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19498
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://chromium-review.googlesource.com/493979
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Write vendor/device id to subsystem vendor/device id
if they are not provided.
BUG=none
BRANCH=none
TEST=none
Change-Id: I64ed5b8ce7f62968437aa4ca47d9f561eb88c2c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd891291ed
Original-Change-Id: I5027331a6adf9109767415ba22dfcb17b35ef54b
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19467
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/493978
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Enable audio:
* Add verb table for ALC286 & ALC298
* Enable virtual channel 1 for DmiVc1 & HdaVc1.
TEST= Build for kblrvp3 as well as kblrvp7. Boot to OS & verified
working of audio on both the boards.
Change-Id: I4f8dac51437704e61bf31ecb6f94224a1a4bf6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af295495c2
Original-Change-Id: Id27e3cf585b93ed4131d7bf3d3b53d3f5404b18e
Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18875
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493976
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Enable/Disable the PCIe ports to match factory BIOS. The port #6
is used for PCIe on the M.2 connector which allows for NVMe SSDs
to function.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ib16d60f88990c8481e2a2a5e180fa7d296910895
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cc558e6223
Original-Change-Id: I8058cbad3da651144545d588c0ae78c5f5e598ac
Original-Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Original-Reviewed-on: https://review.coreboot.org/19446
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/493974
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
It's standard practice in vboot that the FWID consists of
<board_name>.<version_number> (e.g. Google_Kevin.8785.57.0). In fact,
some tools rely on this and cut the string at the first dot to
separate the two.
The current Kconfig default in coreboot instead leads to ugly,
parser-breaking FWIDs like Google_Kevin4.5-1234-5678abcd. This patch
fixes that.
BUG=none
BRANCH=none
TEST=none
Change-Id: Ibbe8a40ccbcba8e4d448eb618b6291d43969a6b1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46f292f9bf
Original-Change-Id: I65cd5285c69e2e485d55a41a65d735f6a2291c16
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19487
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/493970
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
