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UPSTREAM: sb/intel/bd82x6x/finalize: Use register name

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Use register name instead of hex values.

No functional change.

BUG=none
BRANCH=none
TEST=none

Change-Id: If7cb7a02841f960f547eaba62f9455499f6ad593
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c368620d60
Original-Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19545
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498310
This commit is contained in:
Patrick Rudolph 2017-05-03 17:50:00 +02:00 • committed by chrome-bot
commit 7fd3d50676
2 changed files with 3 additions and 2 deletions
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4
src/southbridge/intel/bd82x6x/finalize.c
View file

@ -60,10 +60,10 @@ void intel_pch_finalize_smm(void)
RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
/* Global SMI Lock */
pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4);
/* GEN_PMCON Lock */
pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2));
/* R/WO registers */
RCBA32(0x21a4) = RCBA32(0x21a4);

1
src/southbridge/intel/bd82x6x/pch.h
View file

@ -140,6 +140,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define GEN_PMCON_1 0xa0
#define GEN_PMCON_2 0xa2
#define GEN_PMCON_3 0xa4
#define GEN_PMCON_LOCK 0xa6
#define ETR3 0xac
#define ETR3_CWORWRE (1 << 18)
#define ETR3_CF9GR (1 << 20)