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UPSTREAM: nb/intel/sandybridge/romstage: Use register name

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Use register name instead of hex value.
No functional change.

BUG=none
BRANCH=none
TEST=none

Change-Id: I3ed947b8d353083053e801d555239f2805bfe717
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c31af8e1a
Original-Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19544
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498309
This commit is contained in:
Patrick Rudolph 2017-05-03 17:47:54 +02:00 • committed by chrome-bot
commit d20bd993ee
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/intel/sandybridge/romstage.c
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@ -38,9 +38,9 @@ static void early_pch_init(void)
u8 reg8;
// reset rtc power status
reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3);
reg8 &= ~(1 << 2);
pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8);
}
/* Platform has no romstage entry point under mainboard directory,