erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: nb/intel/sandybridge/early_init: Use register name

Browse source 
Use names instead of magic values.

No functional change.

BUG=none
BRANCH=none
TEST=none

Change-Id: I34861a2a83c9d12211667dd5ea1c8c305ede6eef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44526cd1fc
Original-Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19547
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/498312
This commit is contained in:
Patrick Rudolph 2017-05-03 18:49:28 +02:00 • committed by chrome-bot
commit 37272bed84
1 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/northbridge/intel/sandybridge/early_init.c
View file

@ -30,10 +30,10 @@ static void sandybridge_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
printk(BIOS_DEBUG, " done.\n");