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UPSTREAM: nb/intel/sandybridge/gma: Set up OpRegion in nb code

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Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.

Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values

BUG=none
BRANCH=none
TEST=none

Change-Id: I4dee11445385e7c6189593d8a09558e5cd8b7bac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 281ccca373
Original-Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19310
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/493984
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Patrick Rudolph 2017-04-12 16:55:32 +02:00 • committed by chrome-bot
commit 27ca3d5326
2 changed files with 27 additions and 6 deletions
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27
src/northbridge/intel/sandybridge/gma.c
View file

@ -24,6 +24,8 @@
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <cbmem.h>
#include "chip.h"
#include "sandybridge.h"
@ -649,6 +651,30 @@ static void gma_ssdt(device_t device)
drivers_intel_gma_displays_ssdt_generate(gfx);
}
static unsigned long
gma_write_acpi_tables(struct device *const dev,
unsigned long current,
struct acpi_rsdp *const rsdp)
{
igd_opregion_t *opregion;
global_nvs_t *gnvs;
// FIXME: Replace by common VBT implementation writing to current
opregion = igd_make_opregion();
if (opregion) {
/* GNVS has been already set up */
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs) {
/* IGD OpRegion Base Address */
gnvs->aslb = (u32)(uintptr_t)opregion;
} else {
printk(BIOS_ERR, "Error: GNVS table not found.\n");
}
}
return current;
}
/* called by pci set_vga_bridge function */
static void gma_func0_disable(struct device *dev)
{
@ -676,6 +702,7 @@ static struct device_operations gma_func0_ops = {
.enable = 0,
.disable = gma_func0_disable,
.ops_pci = &gma_pci_ops,
.write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112,

6
src/southbridge/intel/bd82x6x/lpc.c
View file

@ -654,10 +654,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
void *opregion;
/* Calling northbridge code as gnvs contains opregion address. */
opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@ -676,8 +672,6 @@ static void southbridge_inject_dsdt(device_t dev)
chromeos_init_vboot(&(gnvs->chromeos));
#endif
/* IGD OpRegion Base Address */
gnvs->aslb = (u32)opregion;
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);