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UPSTREAM: soc/intel/skylake: Enable SATA ports

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The current implementation is incorrect and is
actually disabling the ports.  Fixes that.

BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
     SATA SSD.

Change-Id: I908c1ab04b6d5fd823a89bf1a1eae3116920e468
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d44d028050
Original-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19553
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/497404
This commit is contained in:
Shelley Chen 2017-05-03 11:24:22 -07:00 • committed by chrome-bot
commit 6b42f2a196
1 changed files with 6 additions and 4 deletions
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10
src/soc/intel/skylake/sata.c
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@ -40,14 +40,16 @@ static void *get_ahci_bar(void)
static void sata_final(device_t dev)
{
void *ahcibar = get_ahci_bar();
u8 port_impl;
u32 port_impl, temp;
dev = PCH_DEV_SATA;
/* Read Ports Implemented (GHC_PI) */
port_impl = read32(ahcibar + 0x0c);
port_impl = ~port_impl & 0x07;
port_impl = read32(ahcibar + 0x0c) & 0x07;
/* Port enable */
pci_write_config8(dev, 0x92, port_impl);
temp = pci_read_config32(dev, 0x92);
temp |= port_impl;
pci_write_config32(dev, 0x92, temp);
}
static struct device_operations sata_ops = {