List of changes -
1. Make GPP_B3 IRQ only pin.
2. Remove redundant GPE option from touchpad device.
BUG=b:397905085
TEST=Verified wake from S0ix using touchpad.
Change-Id: I055a60476e4a37bf74940802157bb9cd30bac3c4
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Manually confgiure the vGPIO's related to CNVi for USB Bluetooth
instead of UART.
Change-Id: I7d6007e40b2edbadeb5611f6cd67df0c1e6ee8a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86565
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO is not connected, so configure it accordingly.
Change-Id: I4b3421f1ab676599ffec6b2f46429ce937704e40
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86564
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems FSP will only automatically configure the vGPIO's for
CNVi Bluetooth if USB 2 Port 7 is used. On this board, USB 2
Port 9 is used, so manually confgiure the vGPIO's related to
CNVi for USB Bluetooth instead of UART.
Change-Id: I8d1c337523450de41f11fc9bfbc9b52825d7311c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard is marked IQ1X0MS, though it is also known as the MS-7988.
The Small Form Factor version was used for this port, though the Mini
Tower seems to use the exact same board. Other systems such as the
ThinkCentre M800, ThinkStation P310, ThinkStation P320, and IdeaCentre
700-25ISH appear to use the same PCB with different configurations of
components.
All the code in this port was originally copied from the Asrock H110M
and then modified to match the actual configuration of the M900. The VBT
was extracted using `intelvbttool -l -v data.vbt` while running version
FWKTBFA of the vendor firmware.
Working:
- Boots to Linux with SeaBIOS 1.16.3
- Boots to Linux with EDK2 (MrChromebox uefipayload_202408)
- Display Ports
- VGA port
- PCIe slots
- Console over serial port
- Front and rear USB 3.0 ports and internal USB2.0 headers
- Front and rear audio jacks
- Internal speaker
- SATA ports 1-4 (5 and 6 are not populated on the M900)
- Hardware monitoring via nct6683 kernel module
- Gigabit Ethernet
- S3 suspend/resume
Unknown/untested:
- M.2 E-key slot
- Parallel port header
- PS/2 Mouse/Keyboard via KB_MS1 header
- TPM
Change-Id: I4e70c9f42c19f130a00170b32ae74b61f0483a22
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This patch removes the HAVE_ACPI_RESUME config option from the Google
Brya mainboard configuration. The Intel Alder Lake SoC does not support
S3 (ACPI sleep state) entry/exit, and attempting S3 validation could
lead to abnormal platform behavior. This change ensures that `_S3` is
not listed as a valid wake source in the DSDT (Differentiated System
Description Table) after booting to the OS.
BUG=b:337274309
TEST=Boot verfied google/trulo.
TEST=Veified that the _S3 name variable is not present in the DSDT ASL.
Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86422
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current SMBIOS for fatcat is missing processor upgrade information.
This patch adds the missing value by enabling kconfig flag
CPU_INTEL_SOCKET_OTHER.
Refer to SMBIOS spec sheet for documentation on cpu socket values:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
Output of dmidecode:
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPU0
Type: Central Processor
Family: Pentium Pro
Manufacturer: GenuineIntel
ID: C0 06 0C 00 FF FB EB BF
Signature: Type 0, Family 6, Model 204, Stepping 0
Flags: ...
Version: Genuine Intel(R) 0000
Voltage: Unknown
External Clock: 100 MHz
Max Speed: 3200 MHz
Current Speed: 3000 MHz
Status: Populated, Enabled
- Upgrade: Unknown
+ Upgrade: Other
BUG=NONE
TEST=Boot and verified that SMBIOS processor upgrade value is correct.
Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Fix USB port assignments/descriptions to match actual topology.
TEST=build/boot Win11 on starlabs/starbook_adl_n. Verify ports
match assignmented in devicetree using USBTreeview.
Change-Id: If0b341f1c5f99b53df8fff69f8a58fa732adbbc4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Unselect LIBGFXINIT to bring these two variants inline with the
others.
Change-Id: If0fdc9ffd391f2710f252be7358d87644a77b36a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
According to the design, the SPI ROM will be replaced
with a 16MB size, so the Kconfig is modified to 16MB.
BUG=b:397372760
TEST=emerge-nissa coreboot and check rom size is 16MB
Change-Id: I3ef1aa2401d44259e4301f65e2ba0ac7b9418bbd
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86501
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the meliks variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:394359785
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MELIKS
Change-Id: Iff5e27ef06a44976c2724751de0f9c6d5cf6eaaf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86373
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Uldrenite will support internal fivr in next phase and using fw_config
to decide the board with internal or external fivr.
BUG=b:394752422
BRANCH=firmware-trulo-15217.771.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally
Change-Id: I14233090f2445461cf422c1257f21556fd745b43
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86303
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Improve SSD reset time by enabling earlier sequencing, save 230ms
BUG=b:397098950
TEST=build and boot normal using NVMe
Change-Id: I2e48a6614e8bded36d03138869b0eba7e1acb567
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This GPIO should be NF2, not NF1.
Change-Id: I012acfa43ada5641b37f38892a1e3bfbc6e74843
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Frostflow is a 2-in-1 device, this sets the SMBIOS enclosure type
properly.
Change-Id: I6c3306270cbc80bb55fb536a1fc51a5546287649
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Cave is a 2-in-1 device, this sets the SMBIOS enclosure type properly.
Change-Id: I8f2ec82c97676aa315c18286b5e2eb94d46004ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Set these to minipc and all-in-one respectively now that these
system types exist, so that the SMBIOS enclosure type is correctly
set vs defaulting to desktop.
Change-Id: I661401dcd7fe348a07e34ace309c0a8b7e0f00eb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Puff variants will now correctly show their SMBIOS type as an
all-in-one (dooly, scout) or a mini-pc (all other variants) rather than
the default desktop type.
Change-Id: Id24ff40f0aacade359f281def8be2a41c752d0d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Jecht variants will now correctly show their SMBIOS type as mini-pc
rather than the default desktop type.
Change-Id: I4f1be147bcfdad6247101db5b5943301466e60ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Fizz variants will now correctly show their SMBIOS type as an
all-in-one (karma) or a mini-pc (all other variants) rather than the
default desktop type.
Change-Id: Ida61c68d3664115ca29cb11e6820edb1496e4709
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86458
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cyan and Kefka are convertible devices, so set them as such so their
SMBIOS type is set correctly, necessary for some Linux tablet drivers.
Change-Id: Ief81c7ba83eb5326dd6199508a3194008dee243b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86457
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Beltino variants will now correctly show their SMBIOS type as an
all-in-one (monroe) or a mini-pc (all other variants) rather than the
default desktop type.
Change-Id: Ia9f17236c415b626fd5d553a453cf43d4145ef41
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86456
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the newly-added SYSTEM_TYPE_ALL_IN_ONE for Buddy variant, and
use that as a discriminator to de-duplicate selections for system
type and HAVE_SPD_IN_CBFS.
Change-Id: I0d28bc496ff6bcfa9947a4d15ed2d8f75cf74ac3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
1. K3KL9L90CM-MGCT (SAMSUNG)
2. H58G66BK8BX067 (HYNIX)
BUG=b:388117663
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I1ca97e28852660cae0352d771e30c9348a5939a0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86477
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Brask devices are all Chromeboxes, so select SYSTEM_TYPE_MINIPC to
ensure the SMBIOS enclosure type is set correctly.
Change-Id: I133a26223ad204dfad67e136cf342d2fb2a7205e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the moxie variant of the kuldax project by
copying the files to a new directory named for the variant.
BUG=b:389391652
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOXIE
Change-Id: Ie2b4888e4150cf2110fbcd57906b3496c97f6712
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Support Fn key on uldrenite emits a scancode of 94 (0x5e) and order the
Kconfig.
BUG=b:394749952
TEST=fn + top row (F1~F12) keys work fine
Change-Id: I92c1bd200f1849a460943bdb96ab122d464a0f40
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86474
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Add SYSTEM_TYPE_SERVER and SYSTEM_TYPE_ALL_INE_ONE; rename
SYSTEM_TYPE_BOX to SYSTEM_TYPE_MINIPC. Map these entries to the
analogous SMBIOS enclosure types.
Follow-on patches will have mainboards select these new SYSTEM_TYPE
entries as appropriate.
Change-Id: I2a35101ccc60daf4863568216ef145c9c701140b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
NovaCustom (Clevo) V5x0TU are two laptops with Intel Core Ultra (Meteor
Lake) series processors.
Two variants (V540TU and V560TU) are supported. Their EC firmware is
different due to keyboard layout changes. On coreboot's side, the only
difference are SMBIOS strings.
Working:
- DDR5 SODIMM in slot RAM2
- M.2 2280 PCIe slots
- Thunderbolt, USB ports
- Video outputs in OS and firmware via FSP GOP
- I2C touchpad, webcam, SD Card reader
- S0ix
- Booting Ubuntu 24.04 with edk2 UefiPayload
- Vboot, TPM measured boot
VBT was extracted from Clevo Insyde firmware, version v1.07.2.
Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82673
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the template files to a new directory named for the guren variant.
BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=None
Change-Id: I23803aaceb122d2b9e3c2215914643593afa1246
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86492
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Both of these boards use the Intel 9560, which does not
support audio offload so configure it accordingly.
Change-Id: Idcdbd7cc83eda50ece74ce823bef60b16b49600c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86502
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Fn key on kanix emits the scancode 94 (0x5e).
BUG=b:384580437
TEST=Build and test on kanix, the fn key works normally
Change-Id: Ia693813dafe1bd35840dfb892827598a7ca9c88f
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85438
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
These are unnecessary because they are the same as the chipset
devicetree defaults.
Change-Id: Id26f09674457720ad56a19b6b0884b8012be9019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86412
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Dirks is a Chromebox device, so select SYSTEM_TYPE_BOX for it. Other
nissa variants will continue to have SYSTEM_TYPE_LAPTOP selected.
BUG=b:389391653
TEST=emerge-nissa coreboot
check CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
check CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y
Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
It will cause suspend to fail to enter S0ix. After discussion
with SOC and HW teams, remove GPP_B5 and B6 as ISH function and
disable ISH on the devicetree.
BUG=b:383696667, b:395005219
TEST=emerge-nissa coreboot
Change-Id: Id3d26f1b604b889f4fdb6e45218f4118499c303e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ic226fd93b431467c7fa3a53140102ff4fd327f40
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86271
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase PL4 power limit values for all Intel PTL-H variants on Fatcat
from 50000 to 65000 to ensure successful boot and adequate performance
with 45W and 65W USB-C adapters. This prevents system bottlenecks when
using lower-wattage power supplies.
BUG=b:395130929
TEST=Verified successful boot with 45W and 65W USB-C travel adapters,
as well as 96W/106W USB-C adapters.
Change-Id: I6073e748e9f8c7317f0ad9a1193699e34703bdba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86388
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Spike Simulator commit 191634d2854d implemented a ns16550 serial device
which puts the base address at 0x10000000.
Tested: Start Spike Simulator and see that coreboot prints onto the UART.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0e3db9d8b141c733bf609f906018096e3594ce83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85852
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
