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mb/google/trulo/var/uldrenite: Add FW_CONFIG probe for fivr

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Uldrenite will support internal fivr in next phase and using fw_config
to decide the board with internal or external fivr.

BUG=b:394752422
BRANCH=firmware-trulo-15217.771.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally

Change-Id: I14233090f2445461cf422c1257f21556fd745b43
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86303
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Su 2025-02-07 00:26:33 +08:00 • committed by Matt DeVillier
commit 71b6248602
2 changed files with 28 additions and 15 deletions
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19
src/mainboard/google/brya/variants/uldrenite/overridetree.cb
View file

@ -3,6 +3,10 @@ fw_config
option CELLULAR_ABSENT 0
option CELLULAR_RW350R 1
end
field EXT_VR 3 3
option EXT_VR_PRESENT 0
option EXT_VR_ABSENT 1
end
field TOUCHSCREEN 4 4
option TOUCHSCREEN_UNKNOWN 0
option TOUCHSCREEN_NONE 1
@ -100,21 +104,6 @@ chip soc/intel/alderlake
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
# Configure external V1P05/Vnn/VnnSx Rails
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 780,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,

24
src/mainboard/google/brya/variants/uldrenite/variant.c
View file

@ -83,3 +83,27 @@ void variant_init(void)
mdelay(RW350R_PERST_DELAY_MS);
gpio_configure_pads(rw350r_perst_pad, ARRAY_SIZE(rw350r_perst_pad));
}
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
/* # Configure external V1P05/Vnn/VnnSx Rails */
config->ext_fivr_settings.configure_ext_fivr = 1;
config->ext_fivr_settings.v1p05_enable_bitmap =
FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0;
config->ext_fivr_settings.vnn_enable_bitmap =
FIVR_ENABLE_ALL_SX;
config->ext_fivr_settings.vnn_sx_enable_bitmap =
FIVR_ENABLE_ALL_SX;
config->ext_fivr_settings.v1p05_supported_voltage_bitmap =
FIVR_VOLTAGE_NORMAL;
config->ext_fivr_settings.vnn_supported_voltage_bitmap =
FIVR_VOLTAGE_MIN_ACTIVE;
config->ext_fivr_settings.v1p05_voltage_mv = 1050;
config->ext_fivr_settings.vnn_voltage_mv = 780;
config->ext_fivr_settings.vnn_sx_voltage_mv = 1050;
config->ext_fivr_settings.v1p05_icc_max_ma = 500;
config->ext_fivr_settings.vnn_icc_max_ma = 500;
printk(BIOS_INFO, "Configured External FIVR\n");
}
}