Change the SSD Enable GPIO to PLTRST, as having it configure to DEEP,
renders the SSD inaccessible on S3 exit as it conflicts with the RTD3
driver.
Change-Id: If4a406af13005ba4532091d0c5c75f5198e04ff4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87213
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New Touchscreen function for Guren360 project.
Touchscreen panel of MUTTO A153728S1Y(11')
/K&D KD116N37-30TE-A002(11')/MUTTO B153797S1Y(12') are the
same IC controller for ILITEK device, and set TOUCHSCREEN_ILIT2901
to value "2".
BUG=b:406168542
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: I3435a8852b1fdb897d5f89c580b5f9bfca03dd8e
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
The code currently unconditionally flushes or invalidates the entire
cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector
for APs and after loading SMM handlers.
This commit modifies this behavior to only perform these cache
operations if the CPU does *not* support self-snooping.
Self-snooping CPUs can maintain cache coherency within the core/
complex more efficiently. CPU with self-snoop enabled does not
necessarily need to perform wbinvd to ensure data written to the
cache is reflected in main memory. Self-snooping CPUs employ a
write-back caching policy, combined with a cache coherence protocol,
to manage data writes and ensure consistency between cache and main
memory.
When the BSP writes the SIPI vector or SMM handlers to memory, other
units within the same CPU that might be caching these regions should
be aware of the updates through the self-snooping mechanism. A full
cache flush or invalidate to ensure cache contains reaches to main
memory might be unnecessary and could negatively impact performance.
By conditionally performing these cache operations based on
`self_snooping_supported()`, we can optimize the boot process for CPUs
that have advanced cache coherency features while maintaining correct
behavior on older or simpler CPUs.
TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce
boot time by ~19-25ms.
Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87182
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The system was failing to boot to the OS when the SD FW config was
set to NONE. This was because the X1 PCIe slot power enable (GPP_A08)
was being configured in `pre_mem_x1slot_pads` only if the SD FW config
was not NONE.
This commit moves the configuration of GPP_A08 to the
`romstage_gpio_table` and sets it to an initial low state. This ensures
that the X1 PCIe slot power is correctly initialized early in the boot
process, regardless of the SD FW config.
The `pre_mem_x1slot_pads` array and its conditional configuration in
`fw_config_configure_pre_mem_gpio` have been removed as they are no
longer needed.
TEST=Able to boot google/fatcat w/ CBI 0x5c9014 (i.e. SD_NONE)
Change-Id: I0f2a2540de30294c30c4f5182dab326a54b4583e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87154
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kconfig options `USE_INTEL_FSP_MP_INIT` and
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` are mutually
exclusive ways for the FSP to handle MP initialization.
This commit updates the `default` condition for
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` to `y if
!USE_INTEL_FSP_MP_INIT`. This ensures that if
`USE_INTEL_FSP_MP_INIT` is enabled,
`USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI` will default
to disabled, preventing potential conflicts in MP initialization.
The explicit `depends on
!USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI`
on `USE_INTEL_FSP_MP_INIT` is no longer strictly necessary due to
this change in the default value, but it is kept for clarity and
to explicitly state the mutual exclusivity.
TEST=Able to choose USE_INTEL_FSP_MP_INIT Kconfig for
google/fatcat.
Change-Id: I9ecc7b50ed6a6b13c4ccde0a49f50a40b606a848
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87161
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.
Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87206
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Even when the identifier of an I2C device doesn't have a '0x' prefix,
it's still interpreted as a hexadecimal number.
Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
In contracts to the ISA and LPC bus, eSPI doesn't support legacy
ISA-style DMA any more, so don't list eSPI as interface in the 'drq'
chapter.
The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI)
Interface Base Specification (for Client and Server Platforms)" revision
1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware
Hub (FWH) are not supported over this interface."
Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87204
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The line length limit in the commit messages is 72 characters, not 75,
so fix the value in the documentation. The 72 characters also matches
what checkpatch checks for.
Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since we need to support both MBVR (MotherBoard Voltage Regulator) and
FIVR (Fully Integrated Voltage Regulator) in this phase, the FIT
setting is initially set to FIVR. This causes MBVR boards to have two
voltage sources, potentially triggering OVP and leading to reboots
during the boot process.
The current build's main source is MBVR, so we want to use fw_config
to dynamically adjust MFIT and MBVR with the current phase devices to
ensure consistency in client devices settings.
Refer to Intel#822618 and set PMC Descriptor Record 7, bit 30
(VCCANA VR Location) accordingly. And then CONFIGURE_DESCRIPTOR is a
temporary workaround for the current phase. In the next phase, we will
choose a specific setting for implementation. If there are any concerns,
we use the board ID to restrict it.
BUG=b:404126972
TEST=boot to ChromeOS
Change-Id: I337574c8c55889ceb49b9f33625feadb48bd8890
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87033
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
These were previously removed, but doing so, slowed down the
brightness keys to approx. 3 seconds.
Re-add them to make them instant.
Change-Id: I1256b57192d2f8987bb476cbcc7fd7e81f314d6d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87200
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These were previously removed, but doing so, slowed down the
brightness keys to approx. 3 seconds.
Re-add them to make them instant.
Change-Id: I3af197cd995bd947c6e72bf5593fc966c85c3e3a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces a new timestamp `TS_DEVICE_INIT_CHIPS` to
specifically mark the start of the `dev_initialize_chips()` function.
Previously, the `TS_DEVICE_ENUMERATE` timestamp was incorrectly
associated with the `bs_dev_init_chips` function.
This patch corrects this by:
- Adding the `TS_DEVICE_INIT_CHIPS` enum and name definition.
- Updating `bs_dev_init_chips` in `src/lib/hardwaremain.c` to use
`TS_DEVICE_INIT_CHIPS`.
- Moving the `TS_DEVICE_ENUMERATE` timestamp addition to the
`bs_dev_enumerate` function where device enumeration actually begins.
This change provides a more accurate and meaningful timestamp for the
early chipset initialization phase.
TEST=Able to build and boot google/fatcat.
```
971:loading FSP-S 836,277 (10,658)
17:starting LZ4 decompress (ignore for x86) 847,297 (11,019)
18:finished LZ4 decompress (ignore for x86) 847,376 (79)
30:early chipset initialization 854,579 (7,203)
17:starting LZ4 decompress (ignore for x86) 863,483 (8,903)
18:finished LZ4 decompress (ignore for x86) 863,490 (6)
17:starting LZ4 decompress (ignore for x86) 875,196 (11,705)
18:finished LZ4 decompress (ignore for x86) 875,237 (41)
954:calling FspSiliconInit 875,344 (107)
955:returning from FspSiliconInit 942,740 (67,396)
962:calling FspMultiPhaseSiInit 942,744 (4)
963:returning from FspMultiPhaseSiInit 1,081,355 (138,610)
31:device enumeration 1,081,708 (352)
40:device configuration 1,085,721 (4,013)
50:device enable 1,091,517 (5,795)
```
Change-Id: Ib6860901c6b1528ec5098fc93240c6e65777642b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
New WFC function for Guren360 project.
ID of Vendor and Product for AZWAVE/AM-3BA5533-B module are 13d3:5533.
1. Add WFC fw_config setting
2. Used USB2 Port7 for WFC
BUG=b:406164678
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Verified with local build bios via command lsusb
for 13d3:5533 and SSFC WFC enable
Change-Id: Ia2ab019fe76c503cc669ebf4aa8b3d7ae72269c1
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The SoC code requires for GPE DW config values to be different.
Assign the default values of PMC GPIO_CONF register as GPIO GPEs
are not used on this platform. Fixes the assertion in
soc/intel/elkhartalke/pmutil.
TEST=Boot Protectli VP2420 to Ubuntu 24.04.
Change-Id: Ibf4a1f52bf970c27d0ca8dd1b1377d6a5e6477f9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This board is the CWWK variant based upon Alder Lake with 2 2.5 GbE
ports. The variants files structure is inspired by
system76/adl/variants structure, adapted for cw-adl-4l-v1.0 board
and the new cw-adlnth-1c2l-v3.0 (named according to original bios
naming).
CPU: Intel N100 or N305
Memory: 1x DDR5-4800 SODIMM (max 16 GB)
NIC: 2x Intel I226-V 2.5 GbE
Expansion:
- M.2 2230 E key
- M.2 2280 M key
- USB 2.0 header
- Fan header
External ports:
- DC power
- 2x Ethernet
- 2x HDMI
- 2x USB 2.0
Working:
- Boots Debian 12 with SeaBIOS and EDK II payloads
- Serial port
- External USB ports
- 1x HDMI
- 2x Intel I226 2.5 GbE NICs
- M.2 ports
- ACPI S3
- Fan (ITE IT8613E) driver IT87 (frankcrawford github fork)
Not tested:
- The second HDMI
- Audio
- S0ix (cw-adl-4l-v1.0 said it's not working)
- Internal USB ports
VBT extracted from vendor UEFI firmware
version F2 (2024-06-26 10:26:38)
was 100% matching the cw-adl-4l-v1.0,
so we kept only one in the tree.
Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69
Signed-off-by: Julian Intronati <julian.intronati@eho.link>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87027
Reviewed-by: Julian Intronati <julian.intronati@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
MSR definition in soc/amd/*/include/soc/msr.h are the same & hence move
them to common header src/include/cpu/amd/msr.h
Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87124
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set the SSD enable GPIO to DEEP reset, so that the SSD is powered
down in S3.
Change-Id: I6cc247e04974d293dfc157a3b459a3fb61e43a7f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Enable DDC so that GOP can read the backlight brightness from EDID. This
avoids FSP repeatedly trying and failing to read it, and also stops the
backlight brightness not being restored correctly in Linux.
Change-Id: Ic05ec3cece911f61347bceb82e5798729dcaecfe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Iee7121aef28618c0877c97cf454dc1a279758c21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and just makes it easier to read.
Change-Id: I89028c87eeab95bf4e7a35471072bb41d02b4e6c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These pins are not used, so configure them accordingly.
Change-Id: If82741382c113b2f05078e0d24690943c9053421
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I237824415c99bf57e9617a37001383cdda4a38e6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These, unlike almost all other Intel platforms, are not configured
automatically on reset, so coreboot needs to handle it.
Change-Id: Ie013ce1769e61fae1622a9cc1a048229fd9d6944
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This quirk was added to turn of the SSD in S3. This is now handled by
the RTD3 driver, so it can be removed.
Change-Id: Iaf6364a0957f95411c11e31c8317e1c4ec5c769f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87166
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Update AMD maintainers lists to reflect current situation
- Remove Ron Minnich as maintainer (at his request)
- Update the Infrastructure owners to reflect the current situation.
Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85883
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This mostly lists things that long-time coreboot contributors already
do. Some of these rules were captured on the wiki. Others were adopted
from other git commit message guideline documents long ago.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic2ba681193e302318934cc2f7f30659eac73d099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75495
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since commit cd48d19836 ("Rename and move util/gitconfig/rebase.sh"),
the script util/gitconfig/rebase.sh was moved to
util/scripts/cross-repo-cherrypick.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibecafd6cca9d312c48cfc8c38ff11e686ee184d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87063
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: Ia724e342651e064ca095f9f3f1153d86f0a73a46
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87159
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards do not support SATA, so this is not needed.
Change-Id: Iff9a30cf2e8b65649440b33f850f07d499baa073
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a non-functional change, and only makes the GPIOs easier to read.
Change-Id: I879819e028b71137010a21ddcc0ee6b1dafb7936
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are not used so configure them accordingly.
Change-Id: I6c4d793210e3c869e4f500b18a1229c5c4d40f60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These pins are not connected, so configure them accordingly.
Change-Id: I3cf06a0945a7793592e6599dfd4048a6114d1563
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add implementation of sku_id function that reports the SKU ID
information by making use of ChromeOS EC host command. This function
can replace redundant sku_id function definitions across boards that
rely on ChromeOS EC host command to report the SKU ID information.
The boards that relying on ChromeOS EC host command for SKU information
without any board specific quirks can select EC_GOOGLE_CHROMEEC_SKUID
to make use of common sku_id function.
Brya, zork, rex, fatcat, brox and dedede boards select
EC_GOOGLE_CHROMEEC_SKUID to use ChromeOS EC sku_id function.
BUG=b:396366352
TEST=Verify zork and brya boot log reports the correct the SKU ID
information
Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
ChromeEC support information for SKU, OEM name and manufacturer name
using EC host commands. Instead of tying it up with SKU ID Kconfig
define a new Kconfig that clearly describes and allow adding support
for SMBIOS APIs based on ChromeEC host command.
BUG=b:396366352
TEST=Verify ec_smbios still compiles for required boards.
Change-Id: I665a3276aa6dc01571657359d17f292efc601d63
Signed-off-by: Aamir Bohra <aamirbohra@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86993
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Consider special requirements for computing cache size in certain SoCs,
such as `soc/amd/glinda`.
Use the helper function to implement SoC-specific logic for computing
cache size.
Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit introduces support for touch functionalities on the
Google Fatcat board( Please see docu # 818597). Changes include:
- Configuration for building with the THC driver
- Support for touchscreen devices in both THC-I2C and THC-SPI modes
- Rework is necessary for touchscreen use in THC-SPI mode on Fatcat
board
- The ELAN BOM37A device is supported in THC-I2C mode
- The ELAN BOM36 device is supported in THC-SPI mode
- Support for the HYNITRON HFW68H touchpad device in THC-I2C mode
- A rework is required to switch the interrupt pad from GPP_A13 to
GPP_F18 for touchpad use in THC-I2C mode
- Introduction of variant-specific touch.h header file
- Wake support from S0ix state for both touchscreen and touchpad
across multiple modes: LPSS-I2C, THC-I2C, and THC-SPI
- PMC GPE DW0 is reconfigured to GPP_F for Touchpad in LPSS mode in
variant.c for wake support
BUG=none
TEST=
1. Set the CBI firmware configuration for touchscreen to
TOUCHSCREEN_LPSS_I2C and/or TOUCHPAD to TOUCHPAD_LPSS_I2C
2. Check the ACPI objects are generated in SSDT
3. The devices should be enumerated under the /sys/class/hidraw
directory
4. The Touchscreen and/or touchpad should function properly
The cursor on the screen should move accordingly
5. Test wake from S0ix state via touchscreen and touchpad inputs
6. Repeat the above for the THC CBI configurations:
touchscreen: TOUCHSCREEN_THC_I2C
touchpad: TOUCHPAD_THC_I2C
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85200
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change addresses an issue in the touch driver where the ACPI _PRW
method was added unconditionally. The ACPI _PRW method should only be
generated when an Interrupt() resource is used in the _CRS method.
When a GpioInt() resource is used instead, the _PRW method is not
required.
The ACPI generation code has been updated to conditionally add the
_PRW method based on whether the wake source is a GPIO interrupt or
an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin
is specified, which is consistent with ACPI requirements.
BUG=none
TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that
has the necessary touch configurations with wake support. Verify that
the THC ACPI tables are correctly generated in the SSDT. If wake_gpio
(i.e. GpioInt()) is used for wake, no _PRW is generated for the device.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87085
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
