The nyan_blaze board will have different BCT .inc files, to be
added/updated later. GPIOs and some devicetree stuff may also differ.
BUG=None
TEST=Built nyan, nyan_big and nyan_blaze.
BRANCH=None
Change-Id: I8b16fc71346cf973983aa046096b79cb83ad4bb6
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/190721
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Moving the cache-as-ram base address to 0xfe000000 will
provide more breathing room in the physical address space.
It will also allow for larger SPI roms in the future.
BUG=chrome-os-partner:27045
BRANCH=baytrail
CQ-DEPEND=CL:*157278
TEST=Built and booted. Suspended and resumes. Vboot works, MRC
settings are being saved as well.
Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190700
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP
status.
BUG=chrome-os-partner:26777
TEST=Manual on Rambi with all patches in sequence:
`crossystem sw_wpsw_boot` prints 0
`flashrom --wp-enable` + reboot
`crossystem sw_wpsw_boot` prints 1
BRANCH=Rambi
Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190097
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set VB_INIT_FLAG_SW_WP_ENABLED according to the status returned by an
optional platform / mainboard function vboot_get_sw_write_protect().
BUG=chrome-os-partner:26777
TEST=Manual on Rambi with all patches in sequence:
`crossystem sw_wpsw_boot` prints 0
`flashrom --wp-enable` and reboot
`crossystem sw_wpsw_boot` prints 1
BRANCH=Rambi
Change-Id: Ifb852d75cc106d10120cfee0a396b0662282051a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190096
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Switching unused pin to GPIO to avoid SPI1 conflicting.
BUG=chrome-os-partner:26701
BRANCH=none
TEST=Built and boot on Nyan
Change-Id: I7de5b8d015f6d02baadd41b1b272dfc49d17c376
Signed-off-by: Neil Chen <neilc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/189970
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Increase available RAM to 16M, register a ram_resource to it
and enter ramstage. Bounce buffer seems to be broken yet,
so assign the payload entry to be above coreboot area at
0x80000000 and it should jump to it.
BUG=None
BRANCH=none
TEST=Boot to minimal payload at 0x80100000 which halts the emulation
Change-Id: I77d6c56f5d4104c95283598b3d6ddabb8e5d0c7b
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186745
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This throws an alignment fault when run in ARMv8 Foundation
model and seems unnecessary, so remove it.
BUG=None
BRANCH=none
TEST=Boot coreboot in foundation model
Change-Id: I2e3aa54502c292958ba44ff4e2e71c27653f2e1a
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186744
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Some 64-bit pointer casts errors related to
DYNAMIC_CBMEM were fixed in a separate patch.
BUG=None
BRANCH=none
TEST=Ran image in foundation model
Change-Id: Ia4cce9bef152e9acd9c897de895b7c293f7d2188
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186742
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Since booting Linux requires that we are running
at EL1 or EL2, transition already from EL3 to EL2.
It is assumed for now that the system implements
all exception levels, which is not a requirement.
BUG=None
BRANCH=none
TEST=Boot to ramstage worked as before and used current_el()
to verify that we are indeed at EL2
Change-Id: I29d8fc830367158cba53703d1dc2f0ad398b9d49
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186741
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This installs a exception vector in bootblock, aborts are now
handled with a register file dump to console for debugging.
BUG=None
BRANCH=none
TEST=Ran image in foundation model, tested some exceptions
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Change-Id: I4cb4d95fc5eb905f8c3c623315a46a00fdbf2677
Reviewed-on: https://chromium-review.googlesource.com/185755
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Marcelo Póvoa <marcelogp@chromium.org>
Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
The DPTF charger particpant device needs to be notified when the
AC state changes so it can re-evaluate the PPCC object and apply
the proper charge rate limit if necessary.
BUG=chromium:349681
TEST=emerge-rambi chromeos-coreboot-rambi
BRANCH=baytrail
Change-Id: I6723754e2fe12862f50709875140fcadcddb18eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189029
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Brad Geltz <brad.geltz@intel.com>
Allow PL1 to be set at the mainboard level.
BUG=chrome-os-partner:26436
TEST=Run DPTF utility, verify specified PL1 settings are still in place.
Modify PL1 settings at mainboard level, verify that changes are
reflected in DPTF utility.
BRANCH=Rambi.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id05701385867420e4d0f129f38dda0d3580abaff
Reviewed-on: https://chromium-review.googlesource.com/189576
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In case we get an invalid thermal reading, let's run the fan
at full speed rather than at low speed. This might impact the
user experiance slightly in cases where the bad reading does
not happen while the system is hot, but it will increase stability
in the cases where the system is actually overheating.
Also, set the critical temperature below tjmax, because otherwise
thermal shutdown by the OS will never be triggered.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BUG=chrome-os-partner:26045
BRANCH=panther, all haswell designs with ITE superIO
TEST=Unable to reproduce bug described in 26045
Change-Id: Iab262f1f17a5dff875c596d9e8d50e4e50ee90f9
Reviewed-on: https://chromium-review.googlesource.com/188556
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
The kernel drivers will soon be updated to use ACPI probing methods, and
now we can put the LPE device into ACPI mode.
BUG=chrome-os-partner:24380
TEST=Verify dev mode FW beep is heard on Rambi platform.
BRANCH=Rambi
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0a2262cb16be8b6da4bcfb557608bc8035249309
Reviewed-on: https://chromium-review.googlesource.com/189371
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Set correct value for SDRAM in Foundation model, map
romstage to run in SRAM and enlarge stack space (in DRAM).
BUG=None
BRANCH=none
TEST=Ran image in foundation model
Change-Id: Id2f7d185fd09f8990c1756ac7ad4569498885ba7
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185754
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
This adds simple bootblock initialization procedures with console
ouput support for the Foundation ARMv8 model. Includes stack
setup, basic caches/tlb/mmu control routines, SCTLR register access
for different exception levels and memset.S code from ARM.
It runs on the Foundation_v8 fast model from arm (see command line
in src/mainboard/emulation/foundation-armv8/Kconfig) until loading
romstage at cbfs_load_stage(), where it currently halts. Code is
debugable using printk only (after console_init) because the
Foundation model does not provide bare metal debugging support (so
adding exception handling and stack/register dump might be useful).
BUG=None
BRANCH=none
TEST=Ran image in foundation model
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Change-Id: I81b12416424a02f24a80924791fc39d9411fa4b4
Reviewed-on: https://chromium-review.googlesource.com/185275
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Marcelo Póvoa <marcelogp@chromium.org>
Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
The PMIC setup code was unconditionally waiting for 10ms after each register
write. It might be possible for there to be an excess of current from lots of
rails switching around at the same time, but we can avoid that with a much
shorter delay in a few strategic places.
This change also moves the write to LDO3 to just under SD1 because LDO3 should
track SD1.
The duration and position for the delays and moving LDO3 were provided by Dan
Coggin at nvidia.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1. Measured a 230 ms decrease in boot time.
BRANCH=None
Change-Id: I14805bf1b6242bdd0b286f37ae7d635c03909677
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/189016
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Daniel Coggin <dcoggin@nvidia.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
These had been set to something fairly random which results in a very slow
clock on the bus itself. The new settings take into consideration the speed
the devices on the bus can run at. The TPM can't seem to handle speeds above
40KHz, but some documentation suggests that it should be able to handle up to
at least 100KHz.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1. Built for big.
BRANCH=None
Change-Id: Iee98957c7e492c7dd08b071aeef3cce75c4a9e56
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/189015
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The divider for the I2C clocks works differently than for other IP blocks and
needs to be set up to reflect that. There's also a large internal divider which
means you have to do extra calculations to determine what the frequency of the
bus itself will be based on the I2C controller clock. The new macro takes the
desired frequency of the bus itself and figures everything else out.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1 using this function to set up the i2c
busses.
BRANCH=None
Change-Id: Ib62a5659bcc0d0e15de41887514ae8efb8c8129a
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/189014
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This allows limiting the CBFS size which is necessary
for building chromeos-bootimage.
BUG=none
BRANCH=none
TEST=emerge-gizmo chromeos-bootimage and run depthcharge
Change-Id: Idc1af152651973864704160ba1076ffa3b0ad749
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188919
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The default SMM region was previously being reserved.
Stop doing that in order to not antagonize certain kernel
loaders and payloads when there are low e820 ram
reservations. Since the default SMM region is not marked
as reserved the region needs backed up and restored on
resume.
BUG=chrome-os-partner:26563
BRANCH=baytrail
TEST=Built and booted. Suspended and resumed. Confirmed no more
e820 reservations at default SMM region. Also noted resume
times are still at ~200ms.
Change-Id: Icf21d40a790b0c1b0b8c2111f779abb996adce56
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189084
There were some missing parenthesis and some extra semicolons which this
change adds and removes, respectively.
BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1. Verified that the same frequency calculated
differently results in the same settings. Before operator precedence would
pull apart the frequency calculation and use the pieces in the wrong order.
BRANCH=None
Change-Id: I843d4ae9f7a2ae362926d94b6b77ef31d350a329
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/189013
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Certain CPUs require the default SMM region to be backed up
on resume after a suspend. The reason is that in order to
relocate the SMM region the default SMM region has to be used.
As coreboot is unaware of how that memory is used it needs to
be backed up. Therefore provide a common method for doing this.
BUG=chrome-os-partner:26563
BRANCH=baytrail
TEST=Confirmed SMM backup region in cbmem. Suspend and Resumed.
Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188716
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Previously the SPI mirroring was using the SMM default
region. If the payload exceeds the SMM default region size
the mirroring won't happen. This causes a slow down. Instead
find a region to mirror into below 4GiB that is marked as
available ram.
Prior to this change 60ms payload times were observed with
current depthcharge builds. With this change the load time is
24ms - 32ms depending on boot type.
BUG=chrome-os-partner:25385
BRANCH=baytrail
TEST=Booted and noted timing.
Change-Id: I201f0fd6cf82f4521e5cb7fafac6ece27951995d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188715
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
PLLP is configured to 408MHz by hardware on T124. Init PLLP is needed only when
to configure it other than 408MHz.
BUG=none
TEST=build nyan and boot kernel.
Change-Id: I8b1abf510ab886e7fddea8864a6d36f12529880e
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/188849
Reviewed-by: Julius Werner <jwerner@chromium.org>
A PLL (Phase-Locked Loop) clock must be locked before it is assigned
as clock source. Otherwise, this clock is unreliable.
Before:
c base(60006080): 48003201, misc(6000608c): 03000000
x base(600060e0): 40009e01, misc(600060e4): 00000000
p base(600060a0): 40002201, misc(600060ac): 00000200
u base(600060c0): 40005001, misc(600060cc): 00000300
d base(600060d0): 48011b0c, misc(600060dc): 40400800
dp base(60006590): 58305a01, misc(60006594): 40000000
After:
c base(60006080): 48003201, misc(6000608c): 03000000
x base(600060e0): 48009e01, misc(600060e4): 00040000
p base(600060a0): 5801980c, misc(600060ac): 00040800
u base(600060c0): 48005001, misc(600060cc): 00400300
d base(600060d0): 48011b0c, misc(600060dc): 40400800
dp base(60006590): 58305a01, misc(60006594): 40000000
BUG=None
TEST=build nyan and boot
Change-Id: I7e5a2eeb5b17f761e0c462ec68a8b221f327fedc
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/188447
Reviewed-by: Julius Werner <jwerner@chromium.org>
The new function "cros_vpd_gets(key, buf, size)" provides an easy and quick way
to retrieve values in ChromeOS VPD section.
BRANCH=none
BUG=none
TEST=Manually added CONFIG_FLASHMAP_OFFSET=0x00100000 in Nayn config,
added a cros_vpd_gets("test", buf, sizeof(buf)) in romstage.c,
emerge-nyan chromeos-coreboot-nyan # builds successfully,
and then get correct VPD values in console output.
Also tried x86 ("emerge-lumpy chromeos-coreboot-lumpy")
Change-Id: I38e50615e515707ffaecdc4c4fae65043541b687
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187430
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
When using LPAE, the address space is split to 2MB blocks. This change makes
the space reserved for DMA consistent with the block size.
TEST=Booted nyan with and without LPAE. Built nyan_big.
BUG=None
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I75c77484f6ca9f23b583ef651956d0265a9b4474
Reviewed-on: https://chromium-review.googlesource.com/188571
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Add a missing "~" so that we mask off just OSC_XOFS field and not the
rest of the register.
BUG=chrome-os-partner:26326
TEST=XHCI sometimes works after LP0.
BRANCH=none
Change-Id: I2df2387dbad6920d36aa2ae5e6cd91e9ec42fa08
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188897
Reviewed-by: Julius Werner <jwerner@chromium.org>
This is a port of coreboot changes from SageBIOS
to support the GizmoSphere Gizmo board target.
A defconfig is avaliable and is similar to other
targets but CONSOLE_CBMEM is not yet functional.
BUG=None
BRANCH=none
TEST=Build with SeaBIOS payload; boot chromeos development image
Change-Id: Ib1ff87d92f0e7cd6c3dbefd6237fef33f185ba86
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188275
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Creates a new CONFIG_DDR3_SOLDERED_DOWN variable to enable
handling proper DDR3 SPD initialization. This patch is from
SageBIOS (forked coreboot) sources and is required for platforms
such as the GizmoSphere Gizmo board.
BUG=None
BRANCH=none
TEST=Run on Gizmo board and check SPD dump being same as SageBIOS
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Change-Id: I28e69d649252f542eb3d20d51ff8af69ae6e394a
Reviewed-on: https://chromium-review.googlesource.com/188273
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Marcelo Póvoa <marcelogp@chromium.org>
Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
The baytrail option rom was not correctly mirroring to the eDP
panel and the HDMI-connected monitor. Therefore, don't suggest
the HDMI monitor in the 0x5f35 video BIOS callback.
BUG=chrome-os-partner:26365
BRANCH=baytrail
TEST=Booted with and without HDMI connected monitor. DEV screen
always showed on eDP panel.
Change-Id: Icd388a9158700e0a9f9f38530297ee13397e7f76
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188731
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fixing the location of the ram oops buffer can lead to certain
kernel and boot loaders being confused when there is a ram
reservation low in the address space. Alternatively provide
a mechanism to allocate the ram oops buffer in cbmem. As cbmem
is usually high in the address space it avoids low reservation
confusion.
The patch uncondtionally provides a GOOG9999 ACPI device with
a single memory resource describing the memory region used for
the ramoops region.
BUG=None
BRANCH=baytrail,haswell
TEST=Built and booted with and w/o dynamic ram oops. With
the corresponding kernel change things behave correctly.
Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186393
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The display driver will not work in the kernel without the
presence of the VBT configuration. This configuration is contained
in the video option rom. Therefore, always load it.
BUG=chrome-os-partner:25885
BRANCH=baytrail
TEST=Built and tested dev as well as normal mode with upstream
patches. eDP panel correctly works still.
Change-Id: Ifd6ff9c7b1e8c18eb5b6683c642a5f0439479074
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188721
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Certain kernel drivers require the presence of option rom
contents because the board's static configuration information
is located within the blob. Therefore, allow a chipset/board to
instruct the pci device handling code to always load but not
necessarily run the option rom.
BUG=chrome-os-partner:25885
BRANCH=baytrail
TEST=Both enabling and not enabling this option shows expected behavior.
Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188720
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Fix the PLLU parameters to match the recommended values from the TRM,
and the values used by the kernel and LP0 blob. This includes adding
support for setting an LFCON value. It appears that changing the PLLU
parameters across suspend/resume causes XHCI stability issues after
resume.
BUG=chrome-os-partner:26326
TEST=XHCI works after LP0 suspend/resume on Nyan.
BRANCH=none
Change-Id: Ia4af12fefeebe607803e7f2f03ee4802367b82c3
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188752
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
This indirectly selects an appropriate PLLX frequency so the main CPUs run as
fast as they can but not faster.
BUG=chrome-os-partner:25467
TEST=Booted on nyan rev1.
BRANCH=None
Change-Id: Ibe61f5e35246b272771debf4fdf90c79b21eb5d0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/188603
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
The PLLX provides the clock for the main cores which can run at different max
frequencies depending on the specific model of Tegra124. This change makes it
possible to select a model which will, in turn, select a frequency for PLLX.
The default is 2GHz which is the lowest maximum frequency.
BUG=chrome-os-partner:25467
TEST=Booted on nyan rev1. Verified that the selected PLLX frequency was 2GHz.
With a change that selects the right model for nyan, verified that the
corresponding frequency was selected.
BRANCH=None
Change-Id: Iee3a615083dee97ad659ff41cbf867af2a0c325d
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/188602
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
