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nyan: big: Set the i2c controller frequencies appropriately.

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These had been set to something fairly random which results in a very slow
clock on the bus itself. The new settings take into consideration the speed
the devices on the bus can run at. The TPM can't seem to handle speeds above
40KHz, but some documentation suggests that it should be able to handle up to
at least 100KHz.

BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1. Built for big.
BRANCH=None

Change-Id: Iee98957c7e492c7dd08b071aeef3cce75c4a9e56
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/189015
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2014-03-05 22:07:41 -08:00 • committed by chrome-internal-fetch
commit afca97a29a
4 changed files with 26 additions and 12 deletions
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4
src/mainboard/google/nyan/bootblock.c
View file

@ -40,8 +40,8 @@ static void set_clock_sources(void)
clock_configure_source(mselect, PLLP, 102000);
/* TODO: is the 1.333MHz correct? This may have always been bogus... */
clock_configure_source(i2c5, CLK_M, 1333);
/* The PMIC is on I2C5 and can run at 400 KHz. */
clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
/* TODO: We should be able to set this to 50MHz, but that did not seem
* reliable. */

15
src/mainboard/google/nyan/mainboard.c
View file

@ -34,10 +34,17 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
clock_configure_source(i2c1, CLK_M, 1333);
clock_configure_source(i2c2, CLK_M, 1333);
clock_configure_source(i2c3, CLK_M, 1333);
clock_configure_source(i2c4, CLK_M, 1333);
/*
* The max98090 codec and the temperature sensor are on I2C1. These
* can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
*/
clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
/*
* The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
* seem to work above around 40 KHz. It's set to run at 100 KHz in the
* kernel.
*/
clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
clock_configure_source(sbc1, PLLP, 5000);

4
src/mainboard/google/nyan_big/bootblock.c
View file

@ -40,8 +40,8 @@ static void set_clock_sources(void)
clock_configure_source(mselect, PLLP, 102000);
/* TODO: is the 1.333MHz correct? This may have always been bogus... */
clock_configure_source(i2c5, CLK_M, 1333);
/* The PMIC is on I2C5 and can run at 400 KHz. */
clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
/* TODO: We should be able to set this to 50MHz, but that did not seem
* reliable. */

15
src/mainboard/google/nyan_big/mainboard.c
View file

@ -34,10 +34,17 @@ static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
clock_configure_source(i2c1, CLK_M, 1333);
clock_configure_source(i2c2, CLK_M, 1333);
clock_configure_source(i2c3, CLK_M, 1333);
clock_configure_source(i2c4, CLK_M, 1333);
/*
* The max98090 codec and the temperature sensor are on I2C1. These
* can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
*/
clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
/*
* The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
* seem to work above around 40 KHz. It's set to run at 100 KHz in the
* kernel.
*/
clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
clock_configure_source(sbc1, PLLP, 5000);