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tegra124: Fix some bugs in the clock configuration macros.

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There were some missing parenthesis and some extra semicolons which this
change adds and removes, respectively.

BUG=chrome-os-partner:25467
TEST=Built and booted on nyan rev1. Verified that the same frequency calculated
differently results in the same settings. Before operator precedence would
pull apart the frequency calculation and use the pieces in the wrong order.
BRANCH=None

Change-Id: I843d4ae9f7a2ae362926d94b6b77ef31d350a329
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/189013
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2014-03-05 21:53:02 -08:00 • committed by chrome-internal-fetch
commit 462e61ad89
1 changed files with 5 additions and 4 deletions
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9
src/soc/nvidia/tegra124/include/soc/clock.h
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@ -1,4 +1,5 @@
/*
* Copyright 2014 Google Inc.
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
@ -192,7 +193,7 @@ enum {
* and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you
* will assign this to a u8, it gets nicely truncated for you.
*/
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / (FREQ)) - 2)
/* Calculate clock frequency value from reference and clock divider value
* The discussion in the book is pretty lacking.
@ -211,18 +212,18 @@ enum {
* Since you multiply denominator * 2 (by NOT shifting it),
* you multiply numerator * 2 to cancel it out.
*/
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2))
#define clock_configure_irregular_source(device, src, freq, src_id) \
clrsetbits_le32(&clk_rst->clk_src_##device, \
CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \
src_id << CLK_SOURCE_SHIFT | \
CLK_DIVIDER(TEGRA_##src##_KHZ, freq));
CLK_DIVIDER(TEGRA_##src##_KHZ, freq))
/* Warning: Some devices just use different bits for the same sources for no
* apparent reason. *Always* double-check the TRM before trusting this macro. */
#define clock_configure_source(device, src, freq) \
clock_configure_irregular_source(device, src, freq, src);
clock_configure_irregular_source(device, src, freq, src)
enum clock_source { /* Careful: Not true for all sources, always check TRM! */
PLLP = 0,