aarch64: Implement basic exception handling
This installs a exception vector in bootblock, aborts are now handled with a register file dump to console for debugging. BUG=None BRANCH=none TEST=Ran image in foundation model, tested some exceptions Signed-off-by: Marcelo Povoa <marcelogp@chromium.org> Change-Id: I4cb4d95fc5eb905f8c3c623315a46a00fdbf2677 Reviewed-on: https://chromium-review.googlesource.com/185755 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Marcelo Póvoa <marcelogp@chromium.org> Commit-Queue: Marcelo Póvoa <marcelogp@chromium.org>
This commit is contained in:
Marcelo Povoa
chrome-internal-fetch
parent
ed1ee57701
commit
69464644ce
6 changed files with 153 additions and 48 deletions
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@ -123,7 +123,7 @@ else
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$(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
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endif
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CFLAGS += \
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CFLAGS += -mstrict-align \
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ldscripts =
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ldscripts += $(src)/arch/aarch64/romstage.ld
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@ -139,15 +139,19 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD
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# Things that appear in every board
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ramstage-y += exception.c
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#ramstage-y += exception_asm.S
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ramstage-y += exception_asm.S
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c
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bootblock-y += cache.c
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bootblock-y += cpu.S
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception_asm.S
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romstage-y += cache.c
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romstage-y += cpu.S
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#romstage-y += div0.c
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romstage-y += exception.c
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romstage-y += exception_asm.S
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romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
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bootblock-y += stages.c
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@ -23,6 +23,7 @@
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#include <arch/cache.h>
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#include <arch/hlt.h>
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#include <arch/stages.h>
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#include <arch/exception.h>
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#include <cbfs.h>
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#include <console/console.h>
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@ -44,6 +45,7 @@ void main(void)
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/* Globally disable MMU, caches, and branch prediction (these should
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* be disabled by default on reset) */
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dcache_mmu_disable();
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write_sctlr(read_sctlr() & ~(SCTLR_A));
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/*
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* Re-enable icache and branch prediction. MMU and dcache will be
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@ -60,7 +62,7 @@ void main(void)
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#ifdef CONFIG_BOOTBLOCK_CONSOLE
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console_init();
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//exception_init();
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exception_init();
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#endif
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entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
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@ -33,98 +33,93 @@
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#include <arch/exception.h>
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#include <console/console.h>
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uint8_t exception_stack[0x100] __attribute__((aligned(8)));
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extern void *exception_stack_end;
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void exception_sync_el0(uint64_t *regs, uint64_t esr);
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void exception_irq_el0(uint64_t *regs, uint64_t esr);
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void exception_fiq_el0(uint64_t *regs, uint64_t esr);
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void exception_serror_el0(uint64_t *regs, uint64_t esr);
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void exception_sync(uint64_t *regs, uint64_t esr);
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void exception_irq(uint64_t *regs, uint64_t esr);
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void exception_fiq(uint64_t *regs, uint64_t esr);
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void exception_serror(uint64_t *regs, uint64_t esr);
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void exception_undefined_instruction(uint32_t *);
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void exception_software_interrupt(uint32_t *);
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void exception_prefetch_abort(uint32_t *);
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void exception_data_abort(uint32_t *);
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void exception_not_used(uint32_t *);
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void exception_irq(uint32_t *);
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void exception_fiq(uint32_t *);
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static void print_regs(uint32_t *regs)
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static void print_regs(uint64_t *regs)
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{
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int i;
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for (i = 0; i < 16; i++) {
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if (i == 15)
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printk(BIOS_ERR, "PC");
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else if (i == 14)
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printk(BIOS_ERR, "LR");
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else if (i == 13)
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printk(BIOS_ERR, "SP");
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else if (i == 12)
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printk(BIOS_ERR, "IP");
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else
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printk(BIOS_ERR, "R%d", i);
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printk(BIOS_ERR, " = 0x%08x\n", regs[i]);
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for (i = 0; i < 31; i+=2) {
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printk(BIOS_ERR, "X%02d = 0x%016llx ", i, regs[i]);
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printk(BIOS_ERR, "X%02d = 0x%016llx\n", i + 1, regs[i + 1]);
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}
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}
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void exception_undefined_instruction(uint32_t *regs)
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void exception_sync_el0(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _undefined_instruction\n");
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printk(BIOS_ERR, "exception _sync_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_software_interrupt(uint32_t *regs)
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void exception_irq_el0(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _software_interrupt\n");
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printk(BIOS_ERR, "exception _irq_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_prefetch_abort(uint32_t *regs)
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void exception_fiq_el0(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _prefetch_abort\n");
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printk(BIOS_ERR, "exception _fiq_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_data_abort(uint32_t *regs)
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void exception_serror_el0(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _data_abort\n");
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printk(BIOS_ERR, "exception _serror_el0 (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_not_used(uint32_t *regs)
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void exception_sync(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _not_used\n");
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printk(BIOS_ERR, "exception _sync (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_irq(uint32_t *regs)
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void exception_irq(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _irq\n");
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printk(BIOS_ERR, "exception _irq (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_fiq(uint32_t *regs)
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void exception_fiq(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _fiq\n");
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printk(BIOS_ERR, "exception _fiq (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_serror(uint64_t *regs, uint64_t esr)
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{
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printk(BIOS_ERR, "exception _serror (ESR = 0x%08llx)\n", esr);
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print_regs(regs);
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die("exception");
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}
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void exception_init(void)
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{
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uint32_t sctlr = read_sctlr();
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//uint32_t sctlr = read_sctlr();
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/* Handle exceptions in ARM mode. */
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//sctlr &= ~SCTLR_TE;
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/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
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//sctlr &= ~SCTLR_V;
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/* Enforce alignment temporarily. */
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write_sctlr(sctlr);
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//write_sctlr(sctlr);
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//extern uint32_t exception_table[];
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//set_vbar((uintptr_t)exception_table);
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//exception_stack_end = exception_stack + sizeof(exception_stack);
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extern uint32_t exception_table[];
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set_vbar((uintptr_t)exception_table);
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printk(BIOS_DEBUG, "Exception handlers installed.\n");
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printk(0, "Exception handlers installed.\n");
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}
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103
src/arch/aarch64/exception_asm.S
Normal file
103
src/arch/aarch64/exception_asm.S
Normal file
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@ -0,0 +1,103 @@
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/*
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* This file is part of the libpayload project.
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*
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* Copyright 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <arch/asm.h>
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.text
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.align 11
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.global exception_table
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exception_table:
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.align 7
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bl exception_prologue
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bl exception_sync_el0
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.align 7
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bl exception_prologue
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bl exception_irq_el0
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.align 7
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bl exception_prologue
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bl exception_fiq_el0
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.align 7
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bl exception_prologue
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bl exception_serror_el0
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.align 7
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bl exception_prologue
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bl exception_sync
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.align 7
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bl exception_prologue
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bl exception_irq
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.align 7
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bl exception_prologue
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bl exception_fiq
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.align 7
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bl exception_prologue
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bl exception_serror
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/*
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* Save state (register file + ELR) to stack
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* and set arguments x0 and x1 for exception call
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*/
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ENTRY(exception_prologue)
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stp x29, x30, [sp, #-16]!
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stp x27, x28, [sp, #-16]!
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stp x25, x26, [sp, #-16]!
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stp x23, x24, [sp, #-16]!
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stp x21, x22, [sp, #-16]!
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stp x19, x20, [sp, #-16]!
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stp x17, x18, [sp, #-16]!
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stp x15, x16, [sp, #-16]!
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stp x13, x14, [sp, #-16]!
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stp x11, x12, [sp, #-16]!
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stp x9, x10, [sp, #-16]!
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stp x7, x8, [sp, #-16]!
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stp x5, x6, [sp, #-16]!
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stp x3, x4, [sp, #-16]!
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stp x1, x2, [sp, #-16]!
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/* FIXME: Don't assume always running in EL3 */
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mrs x1, elr_el3
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stp x1, x0, [sp, #-16]!
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mrs x1, esr_el3
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mov x0, sp
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ret
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ENDPROC(exception_prologue)
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.global exception_stack_end
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exception_stack_end:
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.quad 0
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exception_handler:
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.word 0
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.global set_vbar
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set_vbar:
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msr vbar_el3, x0
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ret
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@ -35,6 +35,7 @@
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#include <arch/stages.h>
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#include <arch/cache.h>
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#include <console/console.h>
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void stage_entry(void)
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{
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@ -19,11 +19,11 @@
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void main(void)
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{
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void *entry;
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void *entry;
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console_init();
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entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
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stage_exit(entry);
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//stage_exit(entry);
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}
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