nyan: big: Only delay when and as long as necessary in the PMIC setup code.
The PMIC setup code was unconditionally waiting for 10ms after each register write. It might be possible for there to be an excess of current from lots of rails switching around at the same time, but we can avoid that with a much shorter delay in a few strategic places. This change also moves the write to LDO3 to just under SD1 because LDO3 should track SD1. The duration and position for the delays and moving LDO3 were provided by Dan Coggin at nvidia. BUG=chrome-os-partner:25467 TEST=Built and booted on nyan rev1. Measured a 230 ms decrease in boot time. BRANCH=None Change-Id: I14805bf1b6242bdd0b286f37ae7d635c03909677 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/189016 Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Daniel Coggin <dcoggin@nvidia.com> Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black
chrome-internal-fetch
parent
afca97a29a
commit
06c4d346de
2 changed files with 74 additions and 63 deletions
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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* Copyright 2014 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -33,42 +33,44 @@ enum {
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struct as3722_init_reg {
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u8 reg;
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u8 val;
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u8 delay;
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};
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static struct as3722_init_reg init_list[] = {
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{AS3722_SDO0, 0x3C},
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{AS3722_SDO1, 0x32},
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{AS3722_SDO2, 0x3C},
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{AS3722_SDO3, 0x00},
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{AS3722_SDO4, 0x00},
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{AS3722_SDO5, 0x50},
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{AS3722_SDO6, 0x28},
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{AS3722_LDO0, 0x8A},
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{AS3722_LDO1, 0x00},
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{AS3722_LDO2, 0x10},
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{AS3722_LDO3, 0x59},
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{AS3722_LDO4, 0x00},
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{AS3722_LDO5, 0x00},
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{AS3722_LDO6, 0x3F},
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{AS3722_LDO7, 0x00},
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{AS3722_LDO9, 0x00},
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{AS3722_LDO10, 0x00},
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{AS3722_LDO11, 0x00},
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{AS3722_SDO0, 0x3C, 1},
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{AS3722_SDO1, 0x32, 0},
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{AS3722_LDO3, 0x59, 0},
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{AS3722_SDO2, 0x3C, 0},
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{AS3722_SDO3, 0x00, 0},
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{AS3722_SDO4, 0x00, 0},
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{AS3722_SDO5, 0x50, 0},
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{AS3722_SDO6, 0x28, 1},
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{AS3722_LDO0, 0x8A, 0},
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{AS3722_LDO1, 0x00, 0},
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{AS3722_LDO2, 0x10, 0},
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{AS3722_LDO4, 0x00, 0},
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{AS3722_LDO5, 0x00, 0},
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{AS3722_LDO6, 0x3F, 0},
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{AS3722_LDO7, 0x00, 0},
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{AS3722_LDO9, 0x00, 0},
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{AS3722_LDO10, 0x00, 0},
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{AS3722_LDO11, 0x00, 1},
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};
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#define AS3722_INIT_REG_LEN ARRAY_SIZE(init_list)
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val)
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
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{
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i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
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udelay(10 * 1000);
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if (delay)
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udelay(500);
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}
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static void pmic_slam_defaults(unsigned bus)
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{
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int i;
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for (i = 0; i < AS3722_INIT_REG_LEN; i++)
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pmic_write_reg(bus, init_list[i].reg, init_list[i].val);
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for (i = 0; i < ARRAY_SIZE(init_list); i++) {
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struct as3722_init_reg *reg = &init_list[i];
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pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
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}
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}
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void pmic_init(unsigned bus)
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@ -84,15 +86,18 @@ void pmic_init(unsigned bus)
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/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
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if (board_id() == 0)
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pmic_write_reg(bus, 0x00, 0x3c);
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pmic_write_reg(bus, 0x00, 0x3c, 1);
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else
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pmic_write_reg(bus, 0x00, 0x50);
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pmic_write_reg(bus, 0x00, 0x50, 1);
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/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
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pmic_write_reg(bus, 0x06, 0x28);
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pmic_write_reg(bus, 0x06, 0x28, 1);
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/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
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pmic_write_reg(bus, 0x12, 0x10);
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/*
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* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
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* regulator.
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*/
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pmic_write_reg(bus, 0x12, 0x10, 1);
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/*
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* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
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@ -101,12 +106,12 @@ void pmic_init(unsigned bus)
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* NOTE: We do this early because doing it later seems to hose the CPU
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* power rail/partition startup. Need to debug.
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*/
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pmic_write_reg(bus, 0x16, 0x3f);
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pmic_write_reg(bus, 0x16, 0x3f, 1);
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/*
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* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
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* the value (register 0x20 bit 4)
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*/
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pmic_write_reg(bus, 0x0c, 0x07);
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pmic_write_reg(bus, 0x20, 0x10);
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pmic_write_reg(bus, 0x0c, 0x07, 0);
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pmic_write_reg(bus, 0x20, 0x10, 1);
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}
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@ -33,42 +33,45 @@ enum {
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struct as3722_init_reg {
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u8 reg;
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u8 val;
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u8 delay;
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};
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static struct as3722_init_reg init_list[] = {
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{AS3722_SDO0, 0x3C},
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{AS3722_SDO1, 0x32},
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{AS3722_SDO2, 0x3C},
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{AS3722_SDO3, 0x00},
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{AS3722_SDO4, 0x00},
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{AS3722_SDO5, 0x50},
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{AS3722_SDO6, 0x28},
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{AS3722_LDO0, 0x8A},
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{AS3722_LDO1, 0x00},
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{AS3722_LDO2, 0x10},
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{AS3722_LDO3, 0x59},
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{AS3722_LDO4, 0x00},
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{AS3722_LDO5, 0x00},
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{AS3722_LDO6, 0x3F},
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{AS3722_LDO7, 0x00},
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{AS3722_LDO9, 0x00},
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{AS3722_LDO10, 0x00},
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{AS3722_LDO11, 0x00},
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{AS3722_SDO0, 0x3C, 1},
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{AS3722_SDO1, 0x32, 0},
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{AS3722_LDO3, 0x59, 0},
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{AS3722_SDO2, 0x3C, 0},
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{AS3722_SDO3, 0x00, 0},
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{AS3722_SDO4, 0x00, 0},
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{AS3722_SDO5, 0x50, 0},
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{AS3722_SDO6, 0x28, 1},
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{AS3722_LDO0, 0x8A, 0},
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{AS3722_LDO1, 0x00, 0},
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{AS3722_LDO2, 0x10, 0},
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{AS3722_LDO4, 0x00, 0},
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{AS3722_LDO5, 0x00, 0},
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{AS3722_LDO6, 0x3F, 0},
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{AS3722_LDO7, 0x00, 0},
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{AS3722_LDO9, 0x00, 0},
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{AS3722_LDO10, 0x00, 0},
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{AS3722_LDO11, 0x00, 1},
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};
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#define AS3722_INIT_REG_LEN ARRAY_SIZE(init_list)
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val)
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
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{
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i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
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udelay(10 * 1000);
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if (delay)
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udelay(500);
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}
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static void pmic_slam_defaults(unsigned bus)
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{
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int i;
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for (i = 0; i < AS3722_INIT_REG_LEN; i++)
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pmic_write_reg(bus, init_list[i].reg, init_list[i].val);
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for (i = 0; i < ARRAY_SIZE(init_list); i++) {
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struct as3722_init_reg *reg = &init_list[i];
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pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
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}
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}
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void pmic_init(unsigned bus)
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@ -83,13 +86,16 @@ void pmic_init(unsigned bus)
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pmic_slam_defaults(bus);
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/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
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pmic_write_reg(bus, 0x00, 0x50);
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pmic_write_reg(bus, 0x00, 0x50, 1);
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/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
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pmic_write_reg(bus, 0x06, 0x28);
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pmic_write_reg(bus, 0x06, 0x28, 1);
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/* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */
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pmic_write_reg(bus, 0x12, 0x10);
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/*
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* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
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* regulator.
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*/
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pmic_write_reg(bus, 0x12, 0x10, 1);
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/*
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* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
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@ -98,12 +104,12 @@ void pmic_init(unsigned bus)
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* NOTE: We do this early because doing it later seems to hose the CPU
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* power rail/partition startup. Need to debug.
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*/
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pmic_write_reg(bus, 0x16, 0x3f);
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pmic_write_reg(bus, 0x16, 0x3f, 1);
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/*
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* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
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* the value (register 0x20 bit 4)
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*/
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pmic_write_reg(bus, 0x0c, 0x07);
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pmic_write_reg(bus, 0x20, 0x10);
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pmic_write_reg(bus, 0x0c, 0x07, 0);
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pmic_write_reg(bus, 0x20, 0x10, 1);
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}
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