Puff variants will now correctly show their SMBIOS type as an
all-in-one (dooly, scout) or a mini-pc (all other variants) rather than
the default desktop type.
Change-Id: Id24ff40f0aacade359f281def8be2a41c752d0d6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Jecht variants will now correctly show their SMBIOS type as mini-pc
rather than the default desktop type.
Change-Id: I4f1be147bcfdad6247101db5b5943301466e60ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Fizz variants will now correctly show their SMBIOS type as an
all-in-one (karma) or a mini-pc (all other variants) rather than the
default desktop type.
Change-Id: Ida61c68d3664115ca29cb11e6820edb1496e4709
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86458
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cyan and Kefka are convertible devices, so set them as such so their
SMBIOS type is set correctly, necessary for some Linux tablet drivers.
Change-Id: Ief81c7ba83eb5326dd6199508a3194008dee243b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86457
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Beltino variants will now correctly show their SMBIOS type as an
all-in-one (monroe) or a mini-pc (all other variants) rather than the
default desktop type.
Change-Id: Ia9f17236c415b626fd5d553a453cf43d4145ef41
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86456
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the newly-added SYSTEM_TYPE_ALL_IN_ONE for Buddy variant, and
use that as a discriminator to de-duplicate selections for system
type and HAVE_SPD_IN_CBFS.
Change-Id: I0d28bc496ff6bcfa9947a4d15ed2d8f75cf74ac3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
1. K3KL9L90CM-MGCT (SAMSUNG)
2. H58G66BK8BX067 (HYNIX)
BUG=b:388117663
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I1ca97e28852660cae0352d771e30c9348a5939a0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86477
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Brask devices are all Chromeboxes, so select SYSTEM_TYPE_MINIPC to
ensure the SMBIOS enclosure type is set correctly.
Change-Id: I133a26223ad204dfad67e136cf342d2fb2a7205e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Create the moxie variant of the kuldax project by
copying the files to a new directory named for the variant.
BUG=b:389391652
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOXIE
Change-Id: Ie2b4888e4150cf2110fbcd57906b3496c97f6712
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Support Fn key on uldrenite emits a scancode of 94 (0x5e) and order the
Kconfig.
BUG=b:394749952
TEST=fn + top row (F1~F12) keys work fine
Change-Id: I92c1bd200f1849a460943bdb96ab122d464a0f40
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86474
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Add SYSTEM_TYPE_SERVER and SYSTEM_TYPE_ALL_INE_ONE; rename
SYSTEM_TYPE_BOX to SYSTEM_TYPE_MINIPC. Map these entries to the
analogous SMBIOS enclosure types.
Follow-on patches will have mainboards select these new SYSTEM_TYPE
entries as appropriate.
Change-Id: I2a35101ccc60daf4863568216ef145c9c701140b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
NovaCustom (Clevo) V5x0TU are two laptops with Intel Core Ultra (Meteor
Lake) series processors.
Two variants (V540TU and V560TU) are supported. Their EC firmware is
different due to keyboard layout changes. On coreboot's side, the only
difference are SMBIOS strings.
Working:
- DDR5 SODIMM in slot RAM2
- M.2 2280 PCIe slots
- Thunderbolt, USB ports
- Video outputs in OS and firmware via FSP GOP
- I2C touchpad, webcam, SD Card reader
- S0ix
- Booting Ubuntu 24.04 with edk2 UefiPayload
- Vboot, TPM measured boot
VBT was extracted from Clevo Insyde firmware, version v1.07.2.
Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82673
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the template files to a new directory named for the guren variant.
BUG=b:397149037
BRANCH=firmware-nissa-15217.B
TEST=None
Change-Id: I23803aaceb122d2b9e3c2215914643593afa1246
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86492
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
coreboot already has a way to configure wakeup from wireless through
the `wifi/generic` driver, so remove these to avoid conflicts.
Change-Id: I744ef37690b7a2478ec29a43b987b43592df2235
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86506
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.
Change-Id: I6d9d6d3b765bba918c08f64458bd1fdad18eff18
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86505
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This method calls STXS and CTXS, which are both serialized so this
method itself does not need to be serialized.
Change-Id: Ia46eaa8746bcff5a57831c14a2845139116b01da
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
This method only returns a package, so it does not need to be
serialized.
Change-Id: I5e61e92b0cffb28aaa070db3e9e8e2ff0e7c4251
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86503
Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Both of these boards use the Intel 9560, which does not
support audio offload so configure it accordingly.
Change-Id: Idcdbd7cc83eda50ece74ce823bef60b16b49600c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86502
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The scope should be closed with `acpigen_write_scope_end`, rather
than `acpigen_pop_len`.
Change-Id: I80df2ee1b51d7dbba85e556bee0fd7513ac933bb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86500
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some upcoming patches run up against the existing limit, which
was added 16 years ago without any justification as to the size.
Bump the size from 10 to 15, to prevent tripping the runtime assertion.
TEST=Tested with rest of patch train
Change-Id: I8362b3a63a23bea0ce47920e5d41cd2535dbc084
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit adds support for VMD (Volume Management Device) in the
Panther Lake SoC. VMD is a feature that allows the management of NVMe
storage devices by abstracting the PCIe root complex. It provides a way
to manage multiple NVMe drives more efficiently.
Changes include:
- Adding VMD to the `min_pci_sleep_states` array in `acpi.c`.
- Updating `chipset.cb` to include the VMD device.
- Disabling the VMD device by default.
- Introducing a new function `fill_fsps_vmd_params`.
- Defining the VMD device and function numbers in `pci_devs.h`.
BUG=b:391083063
TEST=Able to build and boot google/fatcat. Observed that VmdEnable UPD
is disabled in debug FSP logs.
Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Update header files for FSP for Panther Lake platform to version
3015_00, with the previous version being 2454_00.
Changes include:
- Updating UPD Offset in FspmUpd.h and FspsUpd.h
- Adding Sign-of-Life related UPDs in FspmUpd.h
- Adding VMD related UPDs in FspsUpd.h
BUG=b:394189627
TEST=Able to build google/fatcat.
Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86297
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The Fn key on kanix emits the scancode 94 (0x5e).
BUG=b:384580437
TEST=Build and test on kanix, the fn key works normally
Change-Id: Ia693813dafe1bd35840dfb892827598a7ca9c88f
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85438
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In the Panther Lake architecture, each GPIO community functions as a
separate pin control entity. Therefore, when specifying a GPIO
identifier, one should use the community-specific offset, not the number
from the first pad within the GPIO series. This is achieved by selecting
the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within
the Panther Lake SOC Kconfig file.
The numbers within the _CRS GpioInt and GpIo objects in the SSDT should
be offsets within the community. The GPIO identifier employed should
correspond to the offset from the respective community.
Let's take an example. In the fatcat board overridetree.cb,
ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad
starts at 74. It is inside community 1, which starts at 48. The correct
GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal.
Here are two notable changes in the fatcat board SSDT introduced by this
commit.
- ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)
"\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, ,
)
{ // Pin list
- 0x0033
+ 0x002D
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
- ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)
"\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, ,
)
{ // Pin list
- 0x0050
+ 0x003B
}
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
This change is verified via S0ix in Google Fatcat board with
touchscreen/touchpad attached as the wake source.
BUG=none
TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and
ensure that the GPIO number used matches the community offset.
Configure touchscreen/touchpad in THC-i2c mode on factcat board and
enter S0ix and check that it can be waked by touchscreen/touchpad.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit enables Thunderbolt authentication for Panther Lake by
assigning `ioe_tcss_valid_tbt_auth` to the valid_tbt_auth field in
`soc_tcss_ops`.
For the SoC's integrated PD solution, AUX BIAS PAD programming is not
required and has been removed.
TEST=Verified all USB-C ports are functional.
With this patch, \_SB.PCI0.TDM0._DSD exists in the SSDT, containing:
```
Scope (\_SB.PCI0.TDM0)
{
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("c44d002f-69f9-4e7d-a904-a7baabdf43f7"),
Package (0x01)
{
Package (0x02)
{
"IMR_VALID",
One
}
},
ToUUID ("6c501103-c189-4296-ba72-9bf5a26ebe5d"),
Package (0x01)
{
Package (0x02)
{
"WAKE_SUPPORTED",
One
}
}
}
```
Change-Id: I28eac7cfd6511d8680cdae4f830afa73ad201a17
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
These are unnecessary because they are the same as the chipset
devicetree defaults.
Change-Id: Id26f09674457720ad56a19b6b0884b8012be9019
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86412
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch prevents exposing the CPU JTAG GPIO pads. These are
internal GPIO pins used for debugging the SoC and should not be
configurable from the kernel pinctrl driver.
TEST=Able to build and boot google/fatat. Decompile ACPI table
using iasl and ensure CPUJTAG entry not present.
Change-Id: I4d920acb95275fbf72b83b822eddc41829511626
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Dirks is a Chromebox device, so select SYSTEM_TYPE_BOX for it. Other
nissa variants will continue to have SYSTEM_TYPE_LAPTOP selected.
BUG=b:389391653
TEST=emerge-nissa coreboot
check CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
check CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y
Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Add config SYSTEM_TYPE_BOX to allow proper system type selection for
devices like chromebox, mac-mini etc.
Change-Id: I887413cbc09fb0725b2ffd621fe10991b7dbcf6d
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86396
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
It will cause suspend to fail to enter S0ix. After discussion
with SOC and HW teams, remove GPP_B5 and B6 as ISH function and
disable ISH on the devicetree.
BUG=b:383696667, b:395005219
TEST=emerge-nissa coreboot
Change-Id: Id3d26f1b604b889f4fdb6e45218f4118499c303e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ife30f73495d44c98717e147602de10f5a6a89358
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Ic226fd93b431467c7fa3a53140102ff4fd327f40
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86271
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP doesn't support disabling bridges and has no UPDs for that,
they must be enabled in DT to make sure they are properly initialized
during PCI enumeration as expected by the payload (EDK2 for example).
It might be OK to have them set to off when all devices behind the
bridge are also off and FSP disables those secondary devices.
In general something that cannot be hidden/shut off shouldn't be marked
as such, as later stages (payload/OS) might find it active, but
unconfigured.
Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86270
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables the `HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR`
Kconfig option for Alder Lake SoC platform that has support for
CHROMEOS_ENABLE_ESOL.
This allows the eSOL feature (depending upon CHROMEOS_ENABLE_ESOL)
to display a low-battery indicator.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: I8b49a487ca80a2aeeb8b4d8e4c2259217e854444
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86316
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit implements early handling of critical low battery
conditions in the romstage for Alder Lake platforms.
A message is displayed to the user via
ux_inform_user_of_poweroff_operation. A short delay is introduced to
allow the user to see the message. A low battery event is logged.
The system is shut down via the Chrome EC.
This early handling prevents the system from proceeding with
boot (while performing firmware update) if the battery is critically
low and ensures a clean shutdown. This is particularly important for
ChromeOS devices.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: Ib4be86ed17818ee05b7bec0337a90f80017183c2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86227
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements `platform_is_low_battery_shutdown_needed` and
callback for ChromeOS.
- platform_is_low_battery_shutdown_needed: API to check if low battery
shutdown is needed.
BUG=b:339673254
TEST=Verified low battery boot event logging and controlled shutdown.
Change-Id: I119f80a45c045a6095cae98f179c755a2e948e9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit adds the `platform_is_low_battery_shutdown_needed` callback
to the FSP API. This allows platforms to integrate low-battery handling
logic directly into the FSP silicon initialization process. By checking
for critical conditions (e.g., low battery) within this callback after
FSP silicon initialization, the platform can initiate a controlled
shutdown before proceeding with further boot stages, preventing abrupt
shutdowns later in the boot process.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I2d6677d70dea3d24f5a19d70608fd21229a271a0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86226
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit adds a `do_low_battery_poweroff()` function to handle
platform power off due to critically low battery levels.
This provides a standardized way to handle low battery shutdowns across
platforms.
Additionally, the delay to the `do_low_battery_poweroff()` function,
allowing time for the low battery indicator to be displayed before
powering off. The delay is configurable through the
`PLATFORM_LOW_BATTERY_SHUTDOWN_DELAY_SEC` Kconfig option.
Finally, a low battery indicator event is logged using `elog`
before the delay.
This functionality (elog and delay) is enabled when the
`PLATFORM_HAS_LOW_BATTERY_INDICATOR` Kconfig option is selected.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86361
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds low battery indicator bitmap into CBFS. This screen
is displayed when the system detects a critically low battery condition.
The screen displays a logo and can be configured with a custom path.
An option to display an early low battery indicator in text mode is also
included. This early indicator can defer the firmware update.
This feature is controlled by the PLATFORM_HAS_LOW_BATTERY_INDICATOR
Kconfig option.
BUG=b:339673254
TEST=Able to see low-battery user notification in text mode before
memory init. Verified low-battery boot event listed in the eventlog.
Change-Id: I711c53455639b449fe85903139bbc06cdab08d09
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit refactors the logo.bmp inclusion logic to use a helper
macro, `add_bmp_logo_file_to_cbfs`. This centralizes the logic for
adding BMP logo files to the CBFS image and improves code readability.
Change-Id: I135c1f2af02064b72bc1f747336ac98ffdb20842
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86368
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit moves the logo.bmp inclusion logic from
`src/drivers/intel/fsp2_0/Makefile.mk` to `src/lib/Makefile.mk`.
This change centralizes the logo inclusion logic within the `lib`
directory, aligning it with the location of `bmp_logo.c` and making
it independent of the FSP 2.0 driver.
Change-Id: I16ed1cf29b839c25b6ea1c2f10faf3d99dd707c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
