We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217674
Reviewed-by: David Hendricks <dhendrix@chromium.org>
revert this change will cause auron show ERROR
CBFS: ERROR: No file header found at 0x7ff480
and need to add skip ERROR while running suspend_stress_test
But we need to support diff CPU sku, so I revert this change
This reverts commit 5e11145fb3.
BUG=none
TEST=build ok, boot to OS
Change-Id: I29da779f9e0d9a3a8bae46c49250c769a18d0c10
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/216810
Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
The VBIOS DID and the id in config file are inconsistent.
Without this commint, you will need to skip error during
suspend stress test
BUG=chrome-os-partner:31286
BRANCH=none
TEST=build ok, check no ERROR exists in log
Change-Id: Ia73cb4cc4f4b0844a0692f6e760bcc089d64d09c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/216172
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Removing BOOTROM_SDRAM_INIT from Ryu's config
allows the code in sdram.c to handle LPDDR3 init
for all 3 SDRAM vendors now.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BUILD=None
TEST=Built for rush and rush_ryu, booted Ryu to kernel
login AOK (w/Samsung LPDDR3). Booted Rush to where it
tried to load in the Ryu kernel (need to create Rush
boot media). Micron and Hynix SDRAM boards need test
(none here in AZ).
Change-Id: Ieaa880f955e546e707230ba34e09594410c5fd8a
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/215864
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This allows to build coreboot for the mips based board called urara.
BUG=chrome-os-partner:31438
TEST=emerge-urara coreboot succeeds with the proper coreboot image
created. No testing yet.
Change-Id: I420476802fb12e5d02f07998d6c01d8c38b7a83e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
Auron port of Samus commit 715dbb06e9.
BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.
Change-Id: Ie8a660dd139c382929485ff458b5945e8ad72d23
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213957
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
For some reason the veyron config file was checked in as a shell
executable. This patch removes the x bit.
BUG=none
TEST=the file is not executable any more:
$ ls -l configs/config.veyron
-rw-r--r-- 1 vbendeb eng 190 Aug 7 11:39 configs/config.veyron
Change-Id: I6314b58cd4477bc1b4dc44a2651a5f291c23707a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213157
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add the supporting Kconfig options and infrastructure for
performing vboot firmware verification.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Built and ran on ryu into depthcharge noting vboot paths
being taken.
Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211134
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Most things still needs to be filled in, but this will allow us to build boards which use this SOC.
BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot
Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/205069
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Once LPDDR3 init is supported in the ryu romstage, this can
be reverted. Note that this 528MHz BCT has been pre-qualed
by NVIDIA AE's, but will be updated as more tuning is done.
BUG=none
BRANCH=none
TEST=Builds, BCT is in binary, but I have no HW here to test on
Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/208384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The default CBFS size configuration setting is incorrect in case of
Qualcomm SOC targets, as the coreboot blob is much smaller than the
actual bootprom. Note that this size also must match the board fmap
defined in the appropriate depthcharge board directory.
BUG=chromium:394068
TEST=manual
. previously failing to boot coreboot image does not fail to load
depthcharge anymore.
Change-Id: I1b178970b1deee05705490542e4a0c57500379dd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/208146
Reviewed-by: David Hendricks <dhendrix@chromium.org>
In order to make sharing of the location of MTS microcode easier
provide a Kconfig option that is the path to the files.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built rush coreboot.
Change-Id: I36775d0018fc8591d5e77c2943e28a51381713f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207839
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This is a clone of rush for the time being. All the incompatible
bits can be moved later.
BUG=chrome-os-partner:30569
BRANCH=None
TEST=Built coreboot for rush_ryu board
Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207838
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Convert wtm2 board to use the broadwell soc chipset.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2 with haswell and broadwell
CQ-DEPEND=CL:201067
CQ-DEPEND=CL:*164226
Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/201070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/199922
Enable the AS3722 RTC driver for use with event log.
BUG=None
TEST=Built and booted on nyan_big. Built for nyan and nyan_blaze.
BRANCH=nyan
Change-Id: I8c26c304f4bed52d3fe5d2756931075d27bc2c6d
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/197797
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
The coreboot ebuild will take care of placing the blob at the default
location when emerging.
CQ-DEPEND=CL:196414
BUG=chrome-os-partner:28059
TEST=manual
'emerge-storm coreboot' succeeds again
Change-Id: I82c9350eb70f231a0c76b63261518096dbad926c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196406
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
The sbl blobs could not yet be published, they have been moved to a
private location. Update coreboot to pick up the blobs at the correct
place.
BRANCH=None
CQ-DEPEND=CL:195003
BUG=chrome-os-partner:28059
TEST=manual
$ emerge-storm coreboot succeeds
Change-Id: I8c4163bc978307e41c156ef9f7f2a211d57db7a8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/194997
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This enables event logging support for Nyan platforms.
Right now this doesn't do a whole lot. We can add events in
later CLs.
BUG=none
BRANCH=none
TEST=built and booted for Nyan Rev. 1, eventlog gets initialized
if necessary and can be printed by "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Id77a78f55c8bff9ef0ffc7109c8b03c270e8b6b1
Reviewed-on: https://chromium-review.googlesource.com/191200
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
This defines the FMAP offset (currently 0x100000).
BUG=none
BRANCH=none
TEST=booted on Nyan, FMAP can now be found by coreboot
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I1c13e3f8f007729b4570d54392bf5cbf0132a698
Reviewed-on: https://chromium-review.googlesource.com/194477
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This change takes about 8K of space away from the cbfs cache and repurposes
it for the cbmem console buffer. This is a little more than twice the space
we currently need for the bootblock and ROM stage to give us some room to grow
and for extra debug output if needed.
BUG=None
TEST=Built and booted on nyan. Checked the cbmem output.
BRANCH=None
Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/193169
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
A per target config template is required to allow the build system to
produce images. Add a template for storm.
BRANCH=none
BUG=chrome-os-partner:27784
TEST=manual
$ USE=fwserial emerge-storm coreboot
$ grep '^C.*CONSOLE' /build/storm/firmware/coreboot.config
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
CONFIG_CONSOLE_SERIAL=y
CONFIG_CONSOLE_SERIAL_115200=y
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
Change-Id: I9840c1c986788cf36d346d838ff59fe9015ddb07
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193724
Reviewed-by: David Hendricks <dhendrix@chromium.org>
BUG=chrome-os-partner:27094
BRANCH=None
CQ-DEPEND=CL:191031
CQ-DEPEND=CL:191622
TEST=Built and vbooted through depthcharge on nyan.
Change-Id: Idba8f28ed96fb37bb38ab5c05942bdd5bc2efcd3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191535
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
We want the coreboot build produce an image which can be run on the
target, even if the remaining parts of the bootprom (recovery path,
read-write stages, gbb, etc.) are not available yet.
This is achieved by including the Qualcomm SBLs blob in the bootblock.
CQ-DEPEND=CL:193518
BRANCH=None
BUG=chrome-os-partner:27784
TEST=manual
. run the following commands inside chroot to confirm expected image
layout (no actual code is executed on the target yet):
$ emerge-storm coreboot
$ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1
000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff
$ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000
220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a
Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193540
Support for it is broken on ARM and causes memory corruption.
BUG=None
TEST=Built and booted on nyan. Built for daisy, nyan_big and peach_pit.
BRANCH=None
Change-Id: If62c8a4b253ea996f84aa1ce7f789c80bd8d2b9f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/191106
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
BUG=None
TEST=emerge-nyan_blaze chromeos-coreboot-nyan builds OK
Change-Id: I707a5efdbdbc573ef73cd366bb7c90fa7c4e74c2
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/190722
Reviewed-by: Julius Werner <jwerner@chromium.org>
Make the previously partially or completely private configs for bolt, falco,
peppy and samus public.
BUG=None
TEST=Built for each affected board.
BRANCH=None
Change-Id: I8650cc58c804ddf595b44a3feea82b94138bd3c1
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/189781
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Instead of using a hard-coded memory reservation address, allocate
the RAM dynamically for the ram oops buffer.
BUG=chrome-os-partner:26563
BRANCH=baytrail
TEST=Built, booted, crashed. Confirmed pstore had crash. Also, confirmed
ramoops buffer in high memory.
Change-Id: Ic16987e9e54720d807616baf5e40e858fe1604e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188718
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This is a port of coreboot changes from SageBIOS
to support the GizmoSphere Gizmo board target.
A defconfig is avaliable and is similar to other
targets but CONSOLE_CBMEM is not yet functional.
BUG=None
BRANCH=none
TEST=Build with SeaBIOS payload; boot chromeos development image
Change-Id: Ib1ff87d92f0e7cd6c3dbefd6237fef33f185ba86
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188275
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
BRANCH=panther
BUG=none
TEST=Boot systems in question to dev mode, see dev mode screen
Change-Id: I2bd92ac8dc18f660ed69b89ba74f8359278c1923
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183546
Reviewed-by: Mohammed Habibulla <moch@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Mohammed Habibulla <moch@chromium.org>
Tested-by: Mohammed Habibulla <moch@chromium.org>
The name snow goes by in many places in chromeos is daisy. Snow is technically
a variant of daisy and should really be called daisy_snow, but for historical
reasons the daisy board with no variant was used instead. To make it easier to
work with within chromeos, this change renames the snow board to daisy.
BUG=None
TEST=Built for daisy.
BRANCH=None
Change-Id: I569b31bf417db55be91832f15271bea4bc30f163
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183553
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The name pit goes by in many places in chromeos is peach_pit, where peach is
the base name and pit is the name of this particular variant. To make it
easier to work with within chromeos and to make the board names a little less
ambiguous, this change renames the pit board to peach_pit, and from Pit to
Peach Pit.
BUG=None
TEST=Built for peach_pit.
BRANCH=None
Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183552
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The nyan_big mainboard is very similar to nyan, but will be different in a few
ways. For instance, the BCT will be different, and the GPIOs may need to be
configured slightly differently.
This change also adds prefixes to the kconfig variables in "choice" blocks
for both boards since having multiple instances of choice blocks with the same
options confuses kconfig even if all of the instances have mutually exclusive
dependencies.
BUG=None
TEST=Built for nyan and nyan_big.
BRANCH=None
Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183532
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This makes it easy to automatically find the right config based on the board
name.
CQ-DEPEND=CL:180139
BUG=None
TEST=With corresponding eclass change, built for fox wtm2. Attempted to build
for fox baskingridge which is currently broken. Built for daisy.
Change-Id: Iba7e532a34005abfdd81965022608ff30c55efad
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/180170
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The coreboot eclass can append these options to the coreboot config to enable
the serial console.
BUG=None
TEST=Built and booted on nyan and verified that serial was enabled. Built for
all other supported boards except baskingridge which is already broken.
BRANCH=None
Change-Id: I01cfce6dafc866bcc30d98f064a320f2243b4fed
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/178210
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The test on official ChromeOS firmware bitmaps will be very blurry if
the screen resolution is too low (current value, 0x114 = 800x600).
BUG=chrome-os-partner:23766
TEST=emerge-panther chromeos-coreboot-panther
Change-Id: I0b26a3d4a14397fb7e195cda57bc5c1bc713e29e
Signed-off-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179202
Commit-Queue: Mohammed Habibulla <moch@google.com>
Tested-by: Mohammed Habibulla <moch@google.com>
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Instead of choosing between SDRAM configurations for rev0 nyans and everything
else (currently only rev1), we should create a kconfig for each possible config
and put them inside a "choice" block. That way we can have an arbitrarily large
number of choices without them getting to be hard to manage or accidentally not
being mutually exclusive. This also makes the choice of SDRAM config more
explicit instead of it being implied by what rev you're compiled for.
One tradeoff of this approach is that you need to know which config goes with
which rev. Unfortunately we can't decide using the board ID like we can for
most other things because the BCT is consumed by code we don't control before
any of our own code runs.
We default to the slower config for safety's sake, because it will work on
both boards, and because it's the right config for the norrin which we were
going to transition to soon anyway.
Also, we can eliminate the NYAN_IN_A_PIXEL kconfig variable. Alas, we hardly
knew ye.
BUG=None
TEST=Built and booted on both types of nyan.
BRANCH=None
Change-Id: I9a630189e001e95c740c6741057511bf5939fdbb
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/177580
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
