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Include IPQ8064 SBLs code in the coreboot bootblock

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We want the coreboot build produce an image which can be run on the
target, even if the remaining parts of the bootprom (recovery path,
read-write stages, gbb, etc.) are not available yet.

This is achieved by including the Qualcomm SBLs blob in the bootblock.

CQ-DEPEND=CL:193518
BRANCH=None
BUG=chrome-os-partner:27784
TEST=manual

  . run the following commands inside chroot to confirm expected image
    layout (no actual code is executed on the target yet):

   $ emerge-storm coreboot
   $ \od -Ax -t x1 -v   /build/storm/firmware/coreboot.rom  2>/dev/null  | head -1
   000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff
   $ \od -Ax -t x1 -v   /build/storm/firmware/coreboot.rom  | grep 220000
   220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a

Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193540
This commit is contained in:
Vadim Bendebury 2014-04-07 18:59:53 -07:00 • committed by chrome-internal-fetch
commit 64e193974e
3 changed files with 24 additions and 10 deletions
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3
configs/config.storm
View file

@ -1,6 +1,7 @@
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_STORM=y
CONFIG_COREBOOT_ROMSIZE_KB_1024=y
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
# CONFIG_CONSOLE_SERIAL is not set
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_CONSOLE_CBMEM=y
CONFIG_USE_BLOBS=y

8
src/soc/qualcomm/ipq806x/Kconfig
View file

@ -15,11 +15,11 @@ config BOOTBLOCK_ROM_OFFSET
config CBFS_HEADER_ROM_OFFSET
hex "offset of master CBFS header in ROM"
default 0x18000
default 0x221000
config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x18080
default 0x221080
config MBN_ENCAPSULATION
depends on USE_BLOBS
@ -36,7 +36,7 @@ config SBL_BLOB
vendor.
config BOOTBLOCK_BASE
hex "64K bytes left for TZBSP"
default 0x2a010000
hex "256K bytes left for TZBSP"
default 0x2a040000
endif

25
src/soc/qualcomm/ipq806x/Makefile.inc
View file

@ -7,12 +7,25 @@ romstage-y += timer.c
ramstage-y += cbfs.c
ramstage-y += timer.c
ifeq ($(CONFIG_MBN_ENCAPSULATION),y)
ifeq ($(CONFIG_USE_BLOBS),y)
$(objcbfs)/%.bin: $(objcbfs)/%.elf
# Generate the actual coreboot bootblock code
$(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
$(OBJCOPY) -O binary $< $@.prembn
@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $@.prembn $@.tmp
$(OBJCOPY) -O binary $< $@.tmp
@mv $@.tmp $@
endif
# Add MBN header to allow SBL3 to start coreboot bootblock
$(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw
@printf " ADD MBN $(subst $(obj)/,,$(@))\n"
./util/ipqheader/ipqheader.py $(CONFIG_BOOTBLOCK_BASE) $< $@.tmp
@mv $@.tmp $@
# Create a complete bootblock which will start up the system
$(objcbfs)/bootblock.bin: ./$(call strip_quotes,$(CONFIG_SBL_BLOB)) \
$(objcbfs)/bootblock.mbn
@printf " CAT $(subst $(obj)/,,$(@))\n"
@cat $^ > $@.tmp
@mv $@.tmp $@
endif