The code to find the SPD data for the mainboard based on GPIOs
is moved from romstage.c into spd.c.
It relies on the updated pei_data structure from broadwell instead
of the haswell interface.
BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.
Change-Id: Idd9de5701a710be7f59d8e1cd9af2ddea236c261
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213955
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Remove FUI-related code, as it seems not ready for production and makes
life easier with future integrations.
BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.
Change-Id: Ie75cf13fe5b598a17f0b3a6ad458e55f9423125d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213952
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Instead of providing a local copy use the chipset provided one.
BUG=chrome-os-partner:28234
BRANCH=none
TEST=build and boot on samus
Change-Id: I60dd9bbeefbf4298511abec54635c515fc9b1621
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213793
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This introduces a new kconfig variable to select the VBNV backing
store explicitly instead of inferring it from CPU/SoC architecture.
x86 platforms have historically relied only on CMOS to store VBNV
variables, while ARM-based platforms have traditionally relied on
the EC. Neither of those solutions are going to scale well into
the future if/when CMOS disappears and we make ARM-based systems
without an EC.
BUG=chrome-os-partner:29546
BRANCH=none
TEST=compiled for nyan_blaze and samus
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I4a8dadfb6bb666baf1ed4bec98b29c145dc4a1e7
Reviewed-on: https://chromium-review.googlesource.com/213877
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Use the bus number enumerations from funit to make the
pad names and bus numbers consistent and clearer.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: I817a56e879ecc96474128d624dc46c12ebc5c7a8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213492
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The existing cpu_reset does board-wide reset, thus, should be renamed.
BUG=none
BRANCH=none
TEST=Built firmware for Nyans. Ran faft on Blaze.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9
Reviewed-on: https://chromium-review.googlesource.com/212982
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=built ryu, booted to recovery mode OK
Ran TegraShell and could r/w I2C6 regs OK
Change-Id: Ic74e3518ab69ec7b1bc3bc4f637b7b38b85734c9
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/212926
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Able to get sporadic USB communication in depthcharge on ryu.
Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212333
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With non-cacheable memory region and dma range addition, booting from usb
reaches the same point as mmc.
Change-Id: I1083f8de2bfbe9a233d317b29b8fc56f47c7061d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211039
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Use the new funit API to do all the dirty work.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran through depthcharge and into recovery just like
before.
Change-Id: Ief2d81c5569c33a90fc9458d741edef1dcbd8239
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212152
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Currently rush needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With the changes for adding non-cacheable memory range and adding DMA
region, booting from USB reaches same point as MMC.
Change-Id: I6a465eaa77e0d5ab4d5fb22161e88e7a5fd9c4a8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/212193
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These
can be reused for t132 as well.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=Compiles successfuily for nyan, big and blaze
Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211200
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Currently ryu needs a DMA region in order to communicate with
USB devices. Therefore, add that region to the memory map.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With usb added am able to talk to a USB mass storage device
albeit inconsistently.
Change-Id: I6b5c052ccaafce30705349e07639dffbb994901f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212162
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Use funitcfg api for bootblock, romstage as well as ramstage
initialization in rush.
BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully and boots till last known good point.
Change-Id: I8f5801c1c214f05ef9d2ba976838605da2d8b914
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/211766
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Two changes: 1. A44 ID straps use different gpio pins than nyan.
2. A44 uses tristate values instead two state values.
BUG=none
BRANCH=none
TEST=Built and tested on A44 board.
Change-Id: Ia2a4309d3b63b0a94d79465dd727b01fae01e1b9
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/211753
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI device for WLAN and enable GPIO 10 as wake
source in _PRW.
BUG=chrome-os-partner:28234,chrome-os-partner:30671
BRANCH=None
TEST=boot on samus, check for WLAN in /proc/acpi/wakeup
Change-Id: I09b6eeae5bd88ee9d7e0b7e735ed871e8ae6963a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211820
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
nyan blaze fails to boot because tristates of the board id are interpreted in
the reverse order. this change fixes it.
BUG=none
TEST=Booted Blaze to Linux. Built firmware for Storm.
Branch=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I6d81092becb60d12e1cd2a92fc2c261da42c60f5
Reviewed-on: https://chromium-review.googlesource.com/211700
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
I was using the wrong datasheet for these parts. Revert
to the previous geometry settings so they work again.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Change-Id: Ibc4a864d458e5ee5ef69aa4f1db5efe14076422a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211610
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The proto0 storm hardware has TPM reset line wired to the SOC GPIO22
pin instead of the system reset. This causes all kind of TPM behavior
problems and requires frequent power cycles. Adding explicit TPM reset
makes all those problems go away.
BUG=chrome-os-partner:30705, chrome-os-partner:30829
TEST=tried resetting proto0 at different moments during boot up - the
TPM does not fail anymore.
Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211497
Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The name was changed due to review comments misunderstanding, it
should be restored to properly convey what the function does.
BUG=chrome-os-partner:30489
TEST=verified that Storm still properly reports board ID
Change-Id: I4bd63f29afbfaf9f3e3e78602564eb52f63cc487
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211413
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current 2 boards were setting up clocks and enabling
peripherals that apply to the SoC generically. Therefore,
move the common pieces into the SoC code.
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and booted through depthcharge on ryu.
Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211191
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
The I2C pads connected to the EC are pulled to 3.3V. Therefore
the pads need to be configured as open drain.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and booted through depthcharge on ryu
Change-Id: Ia4ad2377d01296235fc7efbba72fa790016c04af
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211135
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Ryu's EC talks proto v3 over i2c. Select the correct protocol.
BUG=chrome-os-partner:31148
BRANCH=None
TEST=Built and ran on ryu. Coreboot can speak to the EC now.
Change-Id: I50e192cd58f7a29103ab94afc002da18822d4080
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211240
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Storm provides three real and two fake gpios. To keep things simple,
define them all as active low and provide appropriate values for the
fake ones.
BUG=chrome-os-partner:30705
TEST=with the appropriate depthcharge change booted proto0, observed
appropriate behavior following the dev switch setting
Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210922
Add the supporting Kconfig options and infrastructure for
performing vboot firmware verification.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Built and ran on ryu into depthcharge noting vboot paths
being taken.
Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211134
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
coreboot already has a reset API. Utilize it by selecting
HAVE_HARD_RESET. The tegra132 boards have to provide the
hard_reset() implementation as that involves board-specific
bits. The tegra132 code then provides a cpu_reset() routine
that just promotes that call to a hard_reset().
For the existing tegra132 boards remove the unnecessary files
from the build.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Ensured hard_reset() does something on Ryu.
Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/211131
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Now that there's a working udelay() in tegra132, upclock
CAM_I2C and SPI1 to the same speeds as used on Nyan.
BUG=chrome-os-partner:30998
BRANCH=rush_ryu
TEST=Built Rush and tested, no nack errors seen.
Change-Id: I58fd03ed3512c2498c793cfe30b0c302e4b0e3d4
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/211043
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No need to define these everywhere, one place will serve all uses.
BUG=none
TEST=compiled various targets without any problem
Change-Id: Iabf31baad6049c758e078727ba3ebe830c3c7684
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210921
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The DRAM include files are not used on Ryu as the BootROM initializes
the memory from the BCT tables.
BUG=None
BRANCH=None
TEST=Built rush_ryu.
Change-Id: If216096ffc9e9836b6d082ad0668640b3eec37b7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210904
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of calling out with function names all the possible
combinations of interface and device provide one call to the
mainboard to configure all the necessary bits.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and ran on rush.
Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210838
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built for ryu.
Change-Id: I2d32d702da38bc0d87a1c159113bba32f4c03407
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210837
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Switch over to the padconfig API for bootblock PAD configurations.
Aside from support code, each entry is 4 bytes. The open coded
calls were 12 bytes each.
BUG=chrome-os-partner:29981
BRANCH=None
TEST=Built and ran on rush. Observed consistent results.
Change-Id: I1d5d38322bda6740a0ea50b89f88b722febdee22
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210836
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of hard coding certain pieces of a board in the common
chipset code provide a way to initialize things early in the
bootblock path. Add a bootblock_mainboard_early_init() function
before console init to performany necessary mainboard initialization
early in the bootblock.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BUG=chrome-os-partner:29981
BRANCH=None
TEST=built both on rush and ryu. rush still behaves the same.
Change-Id: I7d93641dff3a961f120e8f0ec2d959182477ef87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210835
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Workaround for auto shutdown issue on broadwell SKU.
Now we can see C7 transition, and MRC fastboot
BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build ok and boot on samus
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e
Reviewed-on: https://chromium-review.googlesource.com/210870
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Kane Chen <kane.chen@intel.com>
Commit-Queue: Kane Chen <kane.chen@intel.com>
Rush has its EC on SPI, and Ryu has it on I2C, so need both
mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds,
due to romstage.c being in the common tegra132 subdir.
BUG=none
BRANCH=rush_ryu
TEST=Built both rush and rush_ryu images OK. Will try to
boot on Ryu later.
Change-Id: I48d9530697d5669177ecd9ba3c34360197002003
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/210595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
This is a quick port from wtm2 to test on the broadwell Y CRB.
Note that it produces an 8MB image and yet the board has a
16MB SPI flash part. The build tools are not ready to handle
a 16MB image yet so just add 8MB of FFs to the end for now.
BUG=chrome-os-partner:28234
TEST=boot on pearl valley
Change-Id: I849075fc07fa017b5ccca17d0736342a1518db7d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- geometry was incorrect for 8GB modules, should be x32,
so refactor the rest of the geometry to match
- some of the timing values were off, calcualte new values
from the datasheet
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Change-Id: I645f354ef21c5032ab73c66e1ad843136ec93eff
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/210660
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
