rush: Add support for chromeos_ec

BUG=chrome-os-partner:31032
BRANCH=None
TEST=Compiles successfully and ec error fixed while booting.

Change-Id: I02172a30863b7b97892289e880c29f2d71220fda
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/210436
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>

src/mainboard/google/rush/Kconfig

@@ -23,6 +23,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
 	select BOARD_ID_SUPPORT
 	select CHROMEOS
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_SPI
+	select EC_SOFTWARE_SYNC
+	select SPI_FLASH
 	select SOC_NVIDIA_TEGRA132
 	select MAINBOARD_HAS_BOOTBLOCK_INIT
 	select VIRTUAL_DEV_SWITCH
@@ -85,4 +89,8 @@ config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x20
 
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+	hex
+	default 1
+
 endif # BOARD_GOOGLE_RUSH

src/mainboard/google/rush/Makefile.inc

@@ -35,8 +35,6 @@ romstage-y += reset.c
 romstage-y += romstage.c
 romstage-y += sdram_configs.c
 romstage-y += chromeos.c
-romstage-y += ec_dummy.c
 
 ramstage-y += boardid.c
 ramstage-y += mainboard.c
-ramstage-y += ec_dummy.c

src/mainboard/google/rush/mainboard.c

@@ -23,6 +23,7 @@
 #include <soc/clock.h>
 #include <soc/nvidia/tegra132/gpio.h>
 #include <soc/nvidia/tegra132/clk_rst.h>
+#include <soc/nvidia/tegra132/spi.h>
 #include <soc/addressmap.h>
 
 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
@@ -84,11 +85,19 @@ static void init_mmc(void)
 
 }
 
+static void setup_ec_spi(void)
+{
+	struct tegra_spi_channel *spi;
+
+	spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
+}
+
 static void mainboard_init(device_t dev)
 {
 	clock_enable_clear_reset(CLK_L_SDMMC4, 0, CLK_U_SDMMC3, 0, 0, 0);
 
 	init_mmc();
+	setup_ec_spi();
 }
 
 static void mainboard_enable(device_t dev)

src/mainboard/google/rush/romstage.c

@@ -51,6 +51,30 @@ void mainboard_init_tpm_i2c(void)
 	configure_tpm_i2c_bus();
 }
 
+void mainboard_init_ec_spi(void)
+{
+	clock_enable_clear_reset(0, CLK_H_SBC1, 0, 0, 0, 0);
+
+	// SPI1 MOSI
+	pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+	// SPI1 MISO
+	pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+	// SPI1 SCLK
+	pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+	// SPI1 CS0
+	pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
+						 PINMUX_PULL_NONE |
+						 PINMUX_INPUT_ENABLE);
+
+	clock_configure_source(sbc1, CLK_M, 500);
+}
+
 void mainboard_configure_pmc(void)
 {
 }

src/soc/nvidia/tegra132/include/soc/romstage.h

@@ -23,5 +23,6 @@
 void mainboard_configure_pmc(void);
 void mainboard_enable_vdd_cpu(void);
 void mainboard_init_tpm_i2c(void);
+void mainboard_init_ec_spi(void);
 
 #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */

src/soc/nvidia/tegra132/romstage.c

@@ -87,6 +87,7 @@ void romstage(void)
 	printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
 
 	mainboard_init_tpm_i2c();
+	mainboard_init_ec_spi();
 
 	entry = load_ramstage();