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auron: Enable XHCI mode by default

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Auron clone of Samus CL c5ef875f6d.

BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.

Change-Id: I20c7de0606a95cbc20a1b3c018a3318c53c40f4d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213954
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Shawn Nematbakhsh 2014-08-21 12:24:33 -07:00 • committed by chrome-internal-fetch
commit d910468f3d
3 changed files with 8 additions and 4 deletions
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8
payloads/libpayload/configs/config.auron
View file

@ -64,10 +64,10 @@ CONFIG_LP_NVRAM=y
# CONFIG_LP_STORAGE is not set
CONFIG_LP_TIMER_RDTSC=y
CONFIG_LP_USB=y
CONFIG_LP_USB_UHCI=y
CONFIG_LP_USB_OHCI=y
CONFIG_LP_USB_EHCI=y
# CONFIG_LP_USB_XHCI is not set
# CONFIG_LP_USB_UHCI is not set
# CONFIG_LP_USB_OHCI is not set
# CONFIG_LP_USB_EHCI is not set
CONFIG_LP_USB_XHCI=y
CONFIG_LP_USB_HID=y
CONFIG_LP_USB_HUB=y
CONFIG_LP_USB_MSC=y

1
src/mainboard/google/auron/Kconfig
View file

@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select CACHE_ROM
select MARK_GRAPHICS_MEM_WRCOMB
select MONOTONIC_TIMER_MSR
select MAINBOARD_HAS_NATIVE_VGA_INIT
config VBOOT_RAMSTAGE_INDEX
hex

3
src/mainboard/google/auron/devicetree.cb
View file

@ -84,6 +84,9 @@ chip northbridge/intel/haswell
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
# Route all USB ports to XHCI per default
register "xhci_default" = "1"
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA