mainboard/google/ocelot: Update GPIO configuration for SLP_S0_GATE

This commit updates the GPIO configuration for the Ocelot baseboard
variant. It changes the definition of `GPIO_SLP_S0_GATE` from
being not connected (0) to `GPP_C08`. This GPIO will be used as
an indicator for the EC.

References:
  - Schematic version: schematic_1433518

BUG=b:440270606
TEST=Perform an S0ix sequence on the system and verify that the
power state is properly reported on the EC console.

Change-Id: I303322f233824e6980ff6078e62f66eba36203ed
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88875
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/ocelot/variants/baseboard/ocelot/include/baseboard/gpio.h

@@ -17,6 +17,6 @@
  #define EC_SYNC_IRQ	0 /* Not Connected */
 #endif
 #define GPIO_PCH_WP	GPP_D02
-#define GPIO_SLP_S0_GATE	0 /* Not Connected */
+#define GPIO_SLP_S0_GATE	GPP_C08
 
 #endif /* __BASEBOARD_GPIO_H__ */