Add the memory parts: H58G66CK8BX147 (Hynix) in mem_parts_used.txt
,and generate SPD id for the parts.
BUG=none
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I485d8f947b6d8efc5b43ea1ddf1e4187eb4cf2bb
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable LFP1 as it is not present
Change-Id: Ib998bc6df5430d08f9ded4d1e84f5aaa57b8be3d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89097
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFP3 as it is not present
* Change eDP panel colour depth from 18-bit to 24-bit (8 bpc).
* Change POST brightness from 255 to 100.
* Change minimum brightness from 6 to 0.
* Change DPST aggresiveness to 6 to 2.
* Enable PSR
Change-Id: I895fc61dff120e0ae989f45b37c0c5cde3c5e2ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89095
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the ojal variant of the ocelot reference board by copying the
ocelot files to a new directory named for the variant.
BUG=b:437459757
TEST=1. Build emerge-ocelot
2. Run part_id_gen tool without any errors
Change-Id: Ic2fc86d89facae21b9bed898ebe518d316d953da
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Added support for new mainboard configurations, `ptlrvp_chromeec4es`
and `ptlrvp4es`, to the Intel PTLRVP platform. These configurations
extend the existing options for pre-production silicon of the
Panther Lake SoC.
BUG=none
TEST=Build with new configurations to ensure successful compilation and
correct feature selections.
Change-Id: I3f716ab71a97d02b1694858d966f8111f18adff3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88997
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook KBL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: I4d4a41736faac944b3165a56fe5846f24c20f549
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove presence detection flag for the DMIC and internal speakers.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook ADL-N, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: If91c723b6a2fa145c640e06a21198c5ff30a34f2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Remove presence detection flag for the DMIC and internal speakers.
Update the subsystem ID to match that used by the AMI UEFI Firmware.
While we're at it, fix the (non-functional) descriptive flags for
those two verbs as well. Remove unnecessary line continuations.
TEST=build/boot Win11 and Linux on Starbook MTL, verify speaker and
intermal mic working, as well as headphones/jack mic when plugged in.
Change-Id: I7621a6b57fb525892e84d06470eab5a9bdd32065
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89042
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Raptor Lake FSP doesn't seem to honour not touching GPIOs, so set
this to avoid major issues such as the SSD not being recognised and
causing an indefinite hang.
Change-Id: I50edc788c7a4c6ee5a2d74aa76b9e33fb56ed15e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit adds a call to disable_slow_battery_charging() in the
lb_add_boot_mode function.
The logic ensures that charging is disabled if the system is booting in
a normal mode, where neither the LB_BOOT_MODE_LOW_BATTERY nor
LB_BOOT_MODE_OFFMODE_CHARGING flags are set.
This prevents unintended charging by the AP firmware when the device
is not in a low-battery state or booting from off-mode charging to
avoid battery unmanaged health related problem.
TEST=Able to build and boot google/quenbi.
Change-Id: I648dc72a35ad2773f803792248fa87351333828f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89023
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change implements `lb_add_boot_mode` for the `bluey` mainboard,
which adds the platform's boot mode information to the coreboot tables.
This is done by checking the EC (Embedded Controller) to determine if
the battery is below a critical threshold.
If the battery is critically low, the `LB_BOOT_MODE_LOW_BATTERY` flag
is set. This information is then passed to the payload, allowing it to
take specific actions, such as displaying a low-battery charging
screen.
TEST=Able to build and boot the `bluey` mainboard.
Change-Id: I473cec7645954e753e160467aa8b83b67b28ab76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88994
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the new memory support: Hynix H58G56CK8BX146
BUG=b:442335706
BRANCH=firmware-nissa-15217.B
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I8002c2c8e89882f4a705c7aae881544009f84e3b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit updates the GPIO configuration for the Ocelot baseboard
variant. It changes the definition of `GPIO_SLP_S0_GATE` from
being not connected (0) to `GPP_C08`. This GPIO will be used as
an indicator for the EC.
References:
- Schematic version: schematic_1433518
BUG=b:440270606
TEST=Perform an S0ix sequence on the system and verify that the
power state is properly reported on the EC console.
Change-Id: I303322f233824e6980ff6078e62f66eba36203ed
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88875
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new function, disable_slow_battery_charging, to
disable charging on the Bluey mainboard. This function writes a disable
command to the SMBUS chargers, turning off the charging process.
Additionally, this patch makes the following changes to support this
new functionality:
- The charging.c file is now compiled in both the romstage and
ramstage phases.
- The new disable_slow_battery_charging function is declared in
board.h.
- A new charging_status enum is introduced to clearly define the
charging states.
These changes ensure that the system can now properly control charging,
allowing it to be disabled when necessary.
BUG=b:439819922
TEST=Able to build and boot google/quenbi.
Change-Id: Ic0c59e0509889e6d166becf76279718b853021cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89022
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch isolates all charging-related functionality, including
enabling and disabling charging and reading SPMI registers, into a new
dedicated file, charging.c. This improves code organization and
readability by separating concerns, making the codebase easier to
maintain.
Additionally, `enable_battery_charging` is renamed to
`enable_slow_battery_charging` to explicitly state the maximum current
is 1A. The charging enablement logic is also moved to occur before
the AOP firmware is loaded.
TEST=Able to build and boot google/quenbi.
Change-Id: Ieb374cb34814e8eab8dc2ad6f5fb435190167bc7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89021
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is an issue with headset detection on Soundwire audio codec.
Specifically, if the audio is not active (playback/capture is not
ongoing), then 3.5 mm headset detection fails. There is a fix for
Francka (PTL design). Similar implementation is needed for Fatcat.
Port commit a23be7a6fe (mb/google/fatcat/var/francka: Disable ALC721 &
ALC722 clock stop support to francka. This allows the flag to be
overridden via devicetree, instead of relying on the default value in
alc711_slave. It helps fix the missing event issue when plugging or
unplugging the 3.5mm headphone jack.)
BUG=NONE
TEST=After boot to OS, verified headphone detection working using
"getevent" command. Seeing headset jack detected in output:
add device 3: /dev/input/event7
name: "sof-soundwire Headset Jack"
Change-Id: I717f31f8d492bd0b2523c77b7492e46f50de991e
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88986
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Generate RAM ID for MT62F512M32D1DS-023 WT:E
DRAM Part Name ID to assign
MT62F512M32D1DS-023 WT:E 7 (0111)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I6786bff4a03179e3f682ade57d795a449df14bbc
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88925
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the machine shows circle icon instead of G icon in 'Setting'
->'Device'->'View keyboard shortcuts'.
So add MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD to enable G icon.
BUG=b:442310345
BRANCH=none
TEST= Build and boot to OS and enter 'Setting'->'Device'
->'View keyboard shortcuts' to see G icon.
Change-Id: I77e2ce1556ded97c4d146b3e12f751958f31db80
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Disable Enhanced Intel SpeedStep Technology (EIST) to prevent
OS-controlled P-state transitions. This improves consistent CPU
frequency bevahior across all cores, which is critical for real-time
applictaions requiring deterministic performance.
The existing devicetree parameter 'eist_enable' only configures the
IA32_MISC_ENABLE register but does not affect the FSP-S parameter
'Eist'. This results in FSP re-enabling EIST during silicon
initialization, overriding the register setting.
Override the FSP-S 'Eist' parameter at mainboard level rather than
fixing it in SoC code, since devicetree parameters default to 0 when
unset and would disable EIST on boards that rely on FSP defaults.
Change-Id: Ic83246d88607a8ed0c9815e306934bcf0bf8f016
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88965
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable S0ix power states at baseboard level.
TEST=Booted into linux and verified S0ix is disabled:
- FADT Low Power S0 Idle (V5) = 0
Change-Id: I34243137c8b06efa476dda74763d358f88bfe6a5
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88956
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable DPTF for mc_rpl platform. In this context, the DPTF
configuration is removed as well. DPTF is deactivated to improve
realtime performance.
Change-Id: I5f9c2d1d82e9c18eafb9761df87a0709bded5964
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This file contains functions related to PCIe and SMM, and so it's
needed by bootblock and ramstage, and possibly romstage. It's not needed
by SMM, and in a follow-up, the SMI handler will define `smm_region`,
causing a function redefinition error.
As this file isn't needed in SMM, and the SMI handler's function
will work for this board too, as it works for all silicon (it returns
values populated during ramstage, by board/silicon implementations
of the function), drop this compilation unit from SMM.
Change-Id: I0195e7d42b0669d675879fb4d2596aa4607095b9
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88995
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I3ccc64d7bb1a756efe8fc109c51c029a5483c316
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This allows the mainboard code to change FSP-M parameters depending on
parameters that are only known at run time and not at build time.
Mirrors change previous done for Mendocino and newer SoCs.
Change-Id: I6790648da3724a06a127c1cef939366588668440
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
According to the datasheet and the LCD team’s response, increase Touch
IC enable delay time to resolve touch failure after resume.
BUG=b:441010546
TEST=Checked the waveform and suspend stress test, both checked OK.
Meet seconds_system_resume < 0.5 sec, boot time < 1.3 sec.
Change-Id: I778fd79f7bad3ad1873880b7412c0c49dcb40b1f
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change disables the C1E (Enhanced Halt State) power saving feature
by clearing bit 1 in the MSR_POWER_CTL register. Disabling C1E prevents
the processor from automatically transitioning to a lower
voltage/frequency when all cores are halted, improving deterministic
behaviour.
For this platform, disabling C1E is always required, so the direct MSR
approach avoids FSP reliability issues and configuration complexity
that would come with using the existing devicetree "enable_c1e"
parameter.
TEST=Booted into OS and verified register MSR_POWER_CTL Bit 1 cleared:
- Used rdmsr tool: rdmsr 0x1FC showed bit 1 = 0
- Confirmed across all CPU cores
Change-Id: If076f0bb42f3a0d4b8f895703e88eaf145e4a762
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88964
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Remove unused implementation files and declarations:
- Delete ramstage.c containing DPTF power limit configuration
- Remove corresponding ramstage.c reference from Makefile.mk
- Remove unused ADL board ID enumeration in variants.h
- Remove cpu_power_limits structure and variant_update_power_limits()
- Remove variant_devtree_update() function and its weak implementation
The removed code was related to device tree updates and power limit
configurations that are not used by this mainboard.
Change-Id: I1b1c742a4b62022b91de8215d30a4df4f8cf68f0
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88962
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the CPU power limits configuration at the variant level to use 28W
for PL1, PL2. Set PL4 to 64W. This ensures consistent thermal
performance and power management behaviour.
Change-Id: I355f12ad66e9682f3d50356028baea01b42bffa3
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88961
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the moonstone variant of the fatcat reference board by copying
the kinmen files to a new directory named for the variant.
BUG=b:441010542
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_MOONSTONE
2. Run part_id_gen tool without any errors
Change-Id: Iad11c892270f6abc53dee12366691a8c987879f0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88978
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some legacy devices need to have the master bit set in the PCI config
due to old drivers not setting it correctly. Set the master bit if the
feature is enabled via Kconfig switch PCI_ALLOW_BUS_MASTER_ANY_DEVICE.
This implementation is similar to the approach used in an earlier
Siemens platform, as implemented in commit 78ec750610
("mb/siemens/mc_ehl: Enable master bit in PCI config space if allowed").
TEST=Confirmed bus master enabled via lspci after boot.
Change-Id: I6d358ba7147860fd1383abe667a7006d9a30d542
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88963
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable Intel Turbo Boost on this platform as a first step toward
consistent frequency behavior. This platform requires deterministic
performance characteristics rather than dynamic frequency scaling.
TEST=Boot into OS, read MSR 0x1A0 (IA32_MISC_ENABLE) and verify that bit
38 (Turbo Disable) is set.
Change-Id: I6e89cdaaa56b5e5c70461ac67159c0fc3975a429
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Set the active core configuration for the processor on this variant to
use 4 P-cores and 0 E-cores. This ensures that only the performance
cores are enabled, which matches the intended use case for this specific
board variant.
Change-Id: If79b13fea16bcd369feb438aab4ab11dd63d4fab
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88958
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the CPU does not control any fans and the mainboard does not
implement a charger, remove all unnecessary DPTF UPDs. DPTF will be used
for limitting PL1 and PL2 in the future.
Change-Id: I22e1167cb2986f5c56ff6085236792adbb9a19cc
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88954
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
