Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
BUG=b:379008996
BRANCH=none
TEST=build pass and run "storage init" in depthcharge shell on MTK EVB
firmware-shell: storage init
* 0: mtk_mmc
1 devices total
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Change-Id: I82f2a155b810a8b9608d70fe0c015e6054d0be00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87862
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Modify pujjolo vairant codes for type-c port1 display, parade
touch screen, especially for gpio to fit Trulo. Follow the setting of pujjocento.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to pujjolo. Verify functions work.
Change-Id: I285cd33de6e18a2ffb30eb6401c03f6a4b20dc4a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87843
Reviewed-by: Talal Sadak <tsadak@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
WWAN_FCPO == GPP_D6
WWAN_RST == GPP_E17
spec reuqest: 0 < toff <10ms
LTE is controlled by bits 14 and 15 in fw_config, and P sensor
and LTE modules exist at the same time, so we use the same bit
to control whether to load the driver.
BUG=b:419325064,b:417105553
TEST=Confirm the measured WWAN power sequence
Change-Id: Ia978aef2cc721b65618ac78c13930447d1557797
Signed-off-by: Zhaoxiong Lv <lvzhaoxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87841
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
MT8189G variant uses a single PMIC IC (MT6315), whereas the MT8189H
variant uses two PMIC ICs. To ensure driver compatibility, we utilize
the CPU ID and segment ID to accurately determine the required number
of SPMIF instances.
BUG=b:379008996
BRANCH=none
TEST=build pass and boot up normally.
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I07bc21a2026803e76861b27a178d229deca2090a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87854
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
In some SoCs, such as MT8189G/H, different numbers of PMICs are
required. To ensure code reusability and compatibility, it is
necessary to dynamically set this variable. Therefore, spmi_dev_cnt
is changed to a function.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ib8d6306a81c276dceb021ddadec40803fd85019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87853
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
There is no powering-on control in the fingerprint kernel driver.
Follow Rauru to power-on FP MCU in the FW.
BUG=b:401396071
BRANCH=none
TEST=ectool --name=cros_fp version can get the FP FW version.
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Change-Id: I20ff175ee4874c4188b7d07ee57330a9275dcb3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Unit tests should always use a mock ndelay() defined within each test.
Therefore, select ARCH_HAS_NDELAY for ARCH_MOCK.
Change-Id: I2680e37034d4d13058b3e778d72e63fc6ed18313
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This ensures that bridge windows allocate enough space to cover
SR-IOV BARs. Without this Linux will print messages, these messages
may differ depending on the kernel version used.
Debian GNU/Linux 12 (kernel 6.1.0-28-amd64):
pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref]
pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit
pref]
Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic):
pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't
assign; no space
pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to
assign
TEST=Raptorlake-P
Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com>
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34620
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There doesn't seem to be much reason to use absolute paths to the
submodules, other than that it's not needed to change to the original
directory.
In preparation for CB:87824, make use of relative paths and change to
the original directory at the start of each iteration.
Change-Id: Ic74b589d933e6acd882fb9a09461bf7c01952a6f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These variants were missing VBTs necessary for display init, so add
them. VBT files taken from the stock firmware images:
coreboot-Google_Moonbuggy.13324.803.0.bin
coreboot-Google_Scout.13324.645.0.bin
Since all variants now have VBTs, move the selection of
INTEL_GMA_HAVE_VBT to the baseboard.
TEST=build/boot various puff variants, including scout.
Change-Id: I2bb06894fc4df358cc38a4627de9f95289c2c5e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This was kept around to avoid build issues back when the NRI patches
were awaiting review. It is no longer used and to-be-upstreamed code
does not use this define either, so now is a good time to get rid of
it.
Change-Id: Id10d81774b0d679b54d5dc4a15dab5996e3a68c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87832
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The REUT subsequence control register had a different layout in the
Haswell A0 stepping, so it was initially programmed using bitmasks.
However, NRI does not implement support for the A0 stepping because
it is early pre-production silicon that no one should be using, but
the code kept using the bitmasks approach. But we can do better.
Introduce a bitfield for the REUT subsequence control register, and
use it instead of bitmasks. Put the enum for subsequence types next
to the code using it (no reason to have it in the common header, it
is not used anywhere else). And make a helper function that encodes
the number of cachelines in the format expected by the REUT (7 bits
of value, 1 bit for exponential/linear).
Change-Id: I1609ad010e714b0fc47403df7a71e5fc5ae0f5ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87829
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the CPU code exports these PCODE mailbox functions, there is no
reason to retain a copy of them in NRI.
Change-Id: Ic9853cfd6793ecdadf8d2bd15b268f9cf95ba32d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87828
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCODE mailbox is primarily used by CPU code in ramstage. However,
it is also used as part of enabling DDR 2x refresh rate, which is now
implemented in coreboot as part of NRI (native RAM init).
The PCODE mailbox functions in CPU code were not exported at the time
NRI was being developed, so I chose to temporarily copy the functions
into NRI code to make it easier to rebase NRI patches since it avoids
potential merge conflicts. After a few years of rebasing patches, NRI
finally got submitted, so there's no reason to keep duplicate code in
the tree anymore.
Put the relevant PCODE functions into a new file, which gets compiled
for both ramstage (CPU init) and romstage (NRI). The BCLK calibration
function is only used in ramstage so there's no need to move it.
Change-Id: I340625fabc072139b8def254f1ce6b19f360adcd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Group entries by stage and sort groups by stage execution order.
Change-Id: I6e2a53d6555700b48fd3aececdfdb8983554a75a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Ocelot does not support GEN5 NVME Storage. However since ocelot code
was forked from fatcat, these configs exist in coreboot.
Furthermore, the GEN4 NVME GPIOs have changed for ocelot -
1. GPP_B10 to GPP_H18 - GEN4_SSD_PWREN renamed to EN_PP3300_SSD
2. GPP_B09 to GPP_A08 - M2_GEN4_SSD_RESET_N renamed to SSD_PERST_L
BUG=b:419731962
Change-Id: I005d1188138ac7b4bbffa1437bba9aea39aff117
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87804
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Update gpio configuration for GPP_A08, GPP_E17, and GPP_F18 to
match ocelot schematic.
Change GPP_H16 (WWAN_PWR_EN) to GPP_E01 (EN_WWAN_PWR) in fw_config.c.
Change GPP_V06 and GPP_V11 to "No Connect" as they are test points.
Change trace names from "SNDW3_" to "SDW3_" to match names on ocelot
schematic.
BUG=b:412736286
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: I8996dc1b2b0f85490d55a86dc2ca6a90c1604638
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87750
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support the MTK firmware support package (FSP), reserve a 2MB region
in DRAM for loading `mtk_fsp_ramstage.elf` during ramstage.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If153d9746bea8c7faa8f9787029b44192c18899d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87813
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently Francka cannot boot up immediately by pressing power button
when its power state is S5.
This patch fixes the power on process for this scenario.
BUG=b:419406610
BRANCH=none
TEST=Francka boots up immediately by pressing power button in S5.
Change-Id: I52fba7f58faa890955cd07728a6790520df29321
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87807
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Weak symbols don't work as expected when you try to override them from
within the same static library. Static libraries are just archives of
individual objects, and when the linker tries to resolve a symbol
against it it simply uses the implementation from the first object that
has one, weak or not. It does not search through all remaining objects
to see if there's also a strong implementation.
We've had multiple cases in libpayload where builds were incorrectly
using the default implementation rather than an optimized arch-specific
implementation for years due to this issue. To prevent it from
recurring, this patch adds some postprocessing script to the Makefile
that checks for this situation and makes the build fail if it creeps in
again.
Change-Id: I9fcbc9b873901d126322b12954c349c08300369f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
For better readability of the log output, add an empty line between each
iteration of the submodules.
Change-Id: I626b609e9833bffde0f7a5eb101877c6cd83a173
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This modification sets the HDA GPIO pin to NC by default.
Different audio configurations can be enabled via fw_config.
BUG=b:417133565
TEST=emerge-fatcat coreboot, HDA sound cards can be detected.
Change-Id: I0090a68d86de1067697d7efbb64c4638476c64ca
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87810
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables CPU_SUPPORTS_INTEL_TME and TME_KEY_REGENERATION_ON_WARM_BOOT
for Panther Lake, providing hardware memory encryption capabilities.
TEST=Able to build and boot google/francka. Verified TME related
settings inside FSP are now enabled with this patch.
Change-Id: Iedc0d72d00e7e3c5b85916e2de4f020efd5ef024
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit moves the TME configuration into its own static function,
`fill_tme_params`, which is then called from
`fill_fspm_security_params`.
The `TME_KEY_REGENERATION_ON_WARM_BOOT` option is now supported,
allowing a new TME key to be generated on warm reboots.
This feature leverages the `SOC_INTEL_COMMON_BASECODE_RAMTOP`
configuration to determine a memory exclusion range for the new key.
Additionally, disable the `BIOS Guard` UPD as part of security FSP
UPD configuration.
TEST=Able to build and boot google/fatcat. S0ix also works with this
patch.
Change-Id: I1030a25262f1c3c24cf9f4886718689ee2c8155e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87808
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds a new timestamp, `TS_FIRMWARE_SPLASH_RENDERED`
(ID 557), to precisely mark the moment the firmware splash screen has
finished displaying.
The timestamp is recorded in `src/drivers/intel/fsp2_0/silicon_init.c`
within the `do_silicon_init` function. It's conditionally added based on
the platform's configuration:
- For platforms using FSP's native BMP rendering (prior to FSP 2.2, with
`CONFIG(BMP_LOGO)` and without
`CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).
- For platforms where coreboot handles BMP rendering (`CONFIG(BMP_LOGO)`
and `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).
This enhancement provides better visibility into the boot process and
allows for more accurate performance analysis related to splash screen
display time.
BUG=b:418935715
TEST=Able to build and boot google/fatcat. Verified below details in
`cbmem -t`.
```
557:Firmware splash screen rendering finished 47,193,590 (2,235)
```
Change-Id: Ibef967dbc6e224741438e9708b42486ba03d0104
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87812
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set open-drain GPIOs for ChromeOS as input and bias-disable mode. Also
set AP_HDMI_RST_ODL to low, which is the only open-drain output pin.
BUG=b:397102113
BRANCH=none
TEST=build pass
Change-Id: I4375c25768de8f1462c491b2c84b9cf31f118126
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87796
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the CPU little core frequency from 1.6 GHz to 2.0 GHz to
speed up the boot process.
BUG=b:379008996
BRANCH=none
TEST=check little core cpu frequency is 2GHz in kernel by commands
clkdbg() { echo $@ > /proc/clkdbg ; cat /proc/clkdbg ; }
clkdbg fmeter
See the little core CPU frequency:
fm_armpll_ll_ck : 1999968
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I979f44e9340ea5bd733dc7f0fe47af47a4f403b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87795
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for VMODEM and VSRAM_MD buck converters in MT6359. These
buck converters are required for MT8189 to adjust voltage and CPU
frequency.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ifdf43748a139050ec9fba50f918e071dc622a670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87799
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently on power key long press, PMIC will be reset. It would cause
an unwanted reset pulse in the power-off sequence. To match expected
sequence, change PMIC behavior to "force shutdown".
BUG=b:395848137
BRANCH=none
TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse
Change-Id: Ia8fb9f4a1ffe05955fca51a58468ba338ef8e12d
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses
this pin to determine the AP power state. This pin should be set as
early as possible in bootblock.
BUG=b:396030112
BRANCH=none
TEST=reboot pass. `powerinfo` shows S0 in EC console.
Change-Id: Ib7e9eaa19d232a37b3793bcbe268ba021e456ac7
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The commit f66c7c1037 ("util/abuild: Update echo to printf for
consistency") accidentally added whitespaces to the missing_arches
variable, causing the [[ -n "${missing_arches}" ]] check to fail.
The commit c81b08c4ba ("util/abuild: Fix building ChromeOS boards")
intended to fix it, but did it the wrong way.
Now, really fix the problem from the Makefile snippet that is causing
the whitespace issue.
Change-Id: I5e417e851840bad000492bf737fc8e25063fe0c4
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
SMI handler previously did not evaluate input slp_typ parameter and
apparently always acted as S3 was requested.
With the change keyboard is no longer a wakeup source from S4/S5, it is assumed MAINBOARD_EC_S5_WAKE attribute defined in ec.h is correct.
Change-Id: I54c7d7455a6737f731c65e57c91b6457643c7cb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Extracted from coreboot-Google_Teliks.15217.734.0.bin
Change-Id: I2c6b00ab0fc67b651256ec32d4d983b987435010
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87557
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extracted from coreboot-Google_Yaviks.15217.552.0.bin
TEST=build/boot yaviks/yavilla variant with working display.
Change-Id: I775baf4216eef2a60bc1ac034cef3c5c7c38ea69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87556
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Extracted from coreboot-Google_Pujjo.15217.460.0.bin.
TEST=build/boot pujjo1e variant with working display.
Change-Id: I82425bdbbba93197fb7b6f7a866412dc49066cdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
To have the best usage case on 4GBx32 memory sku, the external display
resolution must not exceed 2560x1700. So use the GPP_E13 signal level
to determine x32 memory configuration and apply the corresponding VBT
accordingly.
BUG=b:415850768
TEST=Check the log for the string "Use vbt-uldrenite_x32mem.bin"
Cq-Depend: chrome-internal:8258325
Change-Id: I82a7415b4c99de9278e04f07a9efb0dfa0bf753d
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87654
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These variants were missing VBTs necessary for display init, so add
them. VBT files taken from the stock firmware images:
coreboot-Google_Dood.11297.368.0.bin
coreboot-Google_Foob.11297-169.0.bin
Since all variants other than the baseboard have VBTs, move the
selection of INTEL_GMA_HAVE_VBT to the baseboard and exclude the
octopus board.
TEST=build/boot various ocotpus variants, including dood/foob.
Change-Id: I67655b149de40e3e7f83971780f62cd7fce820c8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87774
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Needed for coolstar's IOM/TCSS drivers under Windows.
TEST=build/boot Win11 on google/screebo
Change-Id: Ib5a288d9b5d259c27f3b3b2b1b7b86e9c0e1f491
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
