{commonlib, drivers}: Track firmware splash screen rendering completion

This commit adds a new timestamp, `TS_FIRMWARE_SPLASH_RENDERED`
(ID 557), to precisely mark the moment the firmware splash screen has
finished displaying.

The timestamp is recorded in `src/drivers/intel/fsp2_0/silicon_init.c`
within the `do_silicon_init` function. It's conditionally added based on
the platform's configuration:

- For platforms using FSP's native BMP rendering (prior to FSP 2.2, with
  `CONFIG(BMP_LOGO)` and without
  `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).
- For platforms where coreboot handles BMP rendering (`CONFIG(BMP_LOGO)`
  and `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`).

This enhancement provides better visibility into the boot process and
allows for more accurate performance analysis related to splash screen
display time.

BUG=b:418935715
TEST=Able to build and boot google/fatcat. Verified below details in
`cbmem -t`.

```
557:Firmware splash screen rendering finished    47,193,590 (2,235)
```

Change-Id: Ibef967dbc6e224741438e9708b42486ba03d0104
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87812
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2025-05-23 06:26:16 +00:00
commit 4c446751c6
2 changed files with 27 additions and 18 deletions

View file

@ -87,6 +87,7 @@ enum timestamp_id {
TS_TPM_ENABLE_UPDATE_END = 554,
TS_ESOL_START = 555,
TS_ESOL_END = 556,
TS_FIRMWARE_SPLASH_RENDERED = 557,
/* 900-940 reserved for vendorcode extensions (900-940: AMD) */
TS_AGESA_INIT_RESET_START = 900,
@ -273,6 +274,7 @@ static const struct timestamp_id_to_name {
TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"),
TS_NAME_DEF(TS_ESOL_START, 0, "started early sign-off life (eSOL) notification"),
TS_NAME_DEF(TS_ESOL_END, 0, "finished early sign-off life (eSOL) notification"),
TS_NAME_DEF(TS_FIRMWARE_SPLASH_RENDERED, 0, "finished rendering splash screen"),
/* AMD related timestamps */
TS_NAME_DEF(TS_AGESA_INIT_RESET_START, TS_AGESA_INIT_RESET_END, "calling AmdInitReset"),

View file

@ -157,16 +157,16 @@ static void do_silicon_init(struct fsp_header *hdr)
fsp_debug_after_silicon_init(status);
fsps_return_value_handler(FSP_SILICON_INIT_API, status);
/*
* Only applies for SoC platforms prior to FSP 2.2 specification:
* If a BMP logo is enabled (`BMP_LOGO`) and the platform is
* configured to skip the FSP for rendering logo bitmap
* (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
* native function to handle BMP logo loading and display.
*/
if (!CONFIG(PLATFORM_USES_FSP2_2) && CONFIG(BMP_LOGO) &&
CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
soc_load_logo_by_coreboot();
/* Only applies for SoC platforms prior to FSP 2.2 specification. */
if (!CONFIG(PLATFORM_USES_FSP2_2) && CONFIG(BMP_LOGO)) {
if (CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
soc_load_logo_by_coreboot();
/*
* This applies regardless of whether FSP or coreboot handled
* the rendering.
*/
timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED);
}
/* Reinitialize CPUs if FSP-S has done MP Init */
if (CONFIG(USE_INTEL_FSP_MP_INIT) && !fsp_is_multi_phase_init_enabled())
@ -216,14 +216,21 @@ static void do_silicon_init(struct fsp_header *hdr)
timestamp_add_now(TS_FSP_MULTI_PHASE_SI_INIT_END);
post_code(POSTCODE_FSP_MULTI_PHASE_SI_INIT_EXIT);
/*
* If a BMP logo is enabled (`BMP_LOGO`) and the platform is
* configured to skip the FSP for rendering logo bitmap
* (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
* native function to handle BMP logo loading and display.
*/
if (CONFIG(BMP_LOGO) && CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
soc_load_logo_by_coreboot();
if (CONFIG(BMP_LOGO)) {
/*
* If a BMP logo is enabled (`BMP_LOGO`) and the platform is
* configured to skip the FSP for rendering logo bitmap
* (`USE_COREBOOT_FOR_BMP_RENDERING`), then call the coreboot
* native function to handle BMP logo loading and display.
*/
if (CONFIG(USE_COREBOOT_FOR_BMP_RENDERING))
soc_load_logo_by_coreboot();
/*
* This applies regardless of whether FSP or coreboot handled
* the rendering.
*/
timestamp_add_now(TS_FIRMWARE_SPLASH_RENDERED);
}
/* Reinitialize CPUs if FSP-S has done MP Init */
if (CONFIG(USE_INTEL_FSP_MP_INIT))