Allow more flexibility by reading and writing to system registers at current
EL. Instead of specifying what _ELx register to write to, code can specify
_current.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles and boots to kernel on ryu
Change-Id: Ic1d9e18e6fc016a04f17621a148e62d6cbd04ce7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214577
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209465
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
In order to ease the process of reading and writing any register at current EL,
provide read_current and write_current assembly macros. These are included in
arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow
the same header file to be included by .c and .S files.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully for ryu
Change-Id: I678ab89c4aa1b08898166e135b5ab2d6453bb5e8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214576
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Add library helpers to access standard arm64 registers. This library also
provides functions to directly read/write register based on current el. So, rest
of the code doesnt need to keep checking the el and call appropriate function
based on that.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Libpayload and depthcharge compile successfully for ryu
Change-Id: I9b63e04aa26a98bbeb34fdef634776d49454ca8d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
The kernel doesn't have the logic for bringing up the plld.
Therefore, configure it in the firmware. The clock used
is an interim value until the display controller sequencing
is fully implemented.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Noted configured freq is close to requested. Also, no
more plld errors observed from the kernel.
Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214841
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Depending on the requested frequency the plld cannot
necessarily obtain the exact clock. Therefore provide the
closest configured frequency as a return value. This is
equivalent to the t124 patch.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Built and noted plld actual value close to requested.
Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214843
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>
These symbols should have been removed with the stack
refactoring. I'm not sure how it was missed.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel with both cpus.
Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/215541
With the latest changes to include stack storage within ramstage, we no longer
need to define Kconfig options for ramstage/exception stacks in arm64.
BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel on ryu
Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214607
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Instruct the SoC to bring up the 2nd core.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Brought up 2nd core in Linux.
Change-Id: I5f5febc4719951188106041f73625231eafe1b08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214778
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Until PSCI is functional the other core still needs to be
brought up in the kernel. The kernel boots these cpus with
the spin table which is just an address in memory to monitor
a jump location.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up secondary core in linux.
Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214777
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Auron port of Samus commit f40e447cee
BUG=chrome-os-partner:31286
TEST=compile ok and make sure the spd index is right on auron
boot to OS
BRANCH=None
Change-Id: Idf8f58dc48ff7dd2481177aa377628cfa032b699
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/214820
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Optionally bring up secondary cpu according to devicetree.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and enabled bringing up second core on ryu.
Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214776
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provides a minimal API for coordinating with the SoC for
bringing up the secondary CPUs. There's no eventloop or
dispatcher currently nor does it do anything proper when
one of the secondary CPUs are brought up. Those decisions
are deferred to the SoC.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu using this API.
Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214775
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
For the secondary CPUs the set of banked registers needs to be
initialized. In the boot CPU path all both the CPU's banked
registers and the global register set is initialized.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu in kernel.
Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214774
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
exception_hwinit() provides a path for just setting the hardware
state. This allows for other CPUs but the boot CPU for setting up
the appropriate vector table.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel.
Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214773
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
No need to pass in the same value for the ttb after just
calling mmu_init(). All current users are setting this once
and forgetting it.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214772
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
To allow setting the entry point for the secondary CPUs
provide a pointer, c_entry, which contains the location
to branc to after setting up the stack.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel on ryu.
Change-Id: Ic2f6c79cde708b24c379345aed1e2cc0760ccad8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214771
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Move the stack seeding out of assembly and into C so the
code in stage_entry.S can more easily be used. The seeding
of the stack doesn't touch at least 256 bytes to account
for current usage at time fo the call.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel on ryu.
Change-Id: I44004220a02b1ff06d27a0555eb4e96d9e213544
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214770
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of defining the stacks by Kconfig options include
the stack sizes for all the CPUs including each of their
exception stacks. This allows for providing each CPU
on startup a stack to work with.
Note: this currently inherits CONFIG_STACK_SIZE from x86 because
of the Kconfig mess of options not being guarded.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into the kernel on ryu.
Change-Id: Ica09dc256e6ce1dd032433d071894af5f445acdb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214669
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Provide a common entry point arm64 cores coming out of reset. Also,
take into account CONFIG_ARM64_CPUS_START_IN_ELx to set the
correct SCTLR_ELx register. The SCR_EL3 initialization was removed
as that can be done in policy code in C later. Part of this refactor
allows for greater code reuse for the secure monitor.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=built and booted to linux on ryu
Change-Id: If16b3f979923ec8add59854db6bad4aaed35e3aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214668
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Depending on the armv8 implementation the cpus could start in
EL1, EL2, or EL3. Therefore allow the SoC to select the appropriate
mode.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: Id063681ef7691097e528c105fffac5d467585e4e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214666
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There are 2 things wrong with the current implementation:
1. the stack isn't guaranteed to be aligned to CONFIG_STACK_SIZE.
2. the stack isn't necessarily CONFIG_STACK_SIZE bytes.
Utilize the smp_processor_id() function to obtain the correct
cpu_info structure to obtain the correct index.
BUG=chrome-os-partner:31545
BRANC=None
TEST=Built and booted.
Change-Id: I2825118e2313dbbf13712a4afdfa05a2e38ee3a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214665
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In order to accomodate MP on arm64 one needs to be able to determine
the current logical processor id. Because it depends on the SoC
implementation the SoC needs to provide this implementation.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: I9511b54b5a1ab340b0f1309b0d9976be68b50903
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214663
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This just removes some unneeded symbols and comments. Additionally,
moved most of the absolute symbols into the individual sections.
Also, aligned data sections to 64 bytes (typical cache line size).
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted through coreboot normally on ryu.
Change-Id: I304e3702247a06507f5f4e23f8776331a3562c68
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214662
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There are 2 cores visible to the OS and both need to be
brought up. Therefore, provide the proper number of cores.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and noted CONFIG_MAX_CPUS=2.
Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214661
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Instead of relying on the encoding of gpio_get_in_tristate_values()
normalize the ids.
BUG=chrome-os-partner:31602
BRANCH=None
TEST=Built and noted correct output w/ coresponding correct device
tree selected in depthcharge.
Change-Id: I7d5449bc14e776fd9faa86af0f80690c3d9ae92d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214840
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Samus has a PD MCU, and should handle PD MCU host events.
BUG=chrome-os-partner:31361
TEST=Manual on Samus. Verify that ACPI Notify routine is called when
host event is sent from EC.
BRANCH=None.
Change-Id: Id40ebd438b3dd60cefc7650f2edc695c589343e9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214860
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add ACPI device for PD MCU, if present. Call Notify routine when the
corresponding EC host event is received.
BUG=chrome-os-partner:31361
TEST=Manual on Samus. Enable EC_ENABLE_PD_MCU_DEVICE, unmask PD MCU host
event, and verify ACPI Notify routine is called when host event is sent
from EC.
BRANCH=None.
Change-Id: I6db61031e434d7ecb211802a4caeaba051e22a28
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214809
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I46257cc71cc3cd1e867edf589ddf09f7990d6784
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209462
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I5105e5277b8072c06bb41b39479373697ef81c67
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209468
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Lin Huang <hl@rock-chips.com>
Commit-Queue: Julius Werner <jwerner@chromium.org>
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: Ib6ee7e3092429a3e47b102751ed6a88aeb9ee7d3
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209429
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Julius Werner <jwerner@chromium.org>
some clock gating and pcie settings are missed in original code
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
verify registers between samus and crb
Change-Id: I931276adb2f2667c4f9e7611acfd709b7232d492
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/214568
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
GD25LQ64C and GD25LB64C have the same ID and settings.
BUG=chrome-os-partner:25907
BRANCH=baytrail
TEST=Boot with GD25LQ64 and check MRC data save/restore works.
Change-Id: I86d1e69552b6000faa9e0523356e27d7e2a6a6db
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/193238
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Increase TZ carveout region size to 4MiB. TTB lives in the first 1MiB of the
trust zone. Rest of the TZ memory can be used by el3 monitor.
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and boots to kernel
Change-Id: I1f25b7b119037cba7055a1bd61997f020a0b1010
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214370
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Fix the alignment for 64-bit systems
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and rmodule load and run for arm64 works fine
Change-Id: I7fcb1683d760b96307759b7d44d8770dd49a02e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214326
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Apparently when I originally wrote this I confused myself to no end.
The code/data of an rmodule has a set memory size which is associated
with the .payload section. The relocation entries may increase the
overall footprint of the memory size if the rmodule has no bss but
a lot of relocations. Therefore, just compare relocation entries size
plus the file size of the .payload section with the memory size of the
paylod section. The .empty section is added only when we have not met
the final target size.
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and the elf.rmod created is verified using readelf
and objdump
Change-Id: I67d8c1267b2216786019eadc02f48b6502026602
Author: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214324
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
The sh_flags for a 64-bit section header entry are 64-bit in size. Correct
this.
BUG=chrome-os-partner:31615
BRANCH=None
TEST=Compiles successfully and the elf.rmod created is verified using readelf
and objdump
Change-Id: I3fd2c19116c375f7321ae83d70e8f20509c6f4c1
Author: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/214323
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
Auron port of Samus commit 715dbb06e9.
BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.
Change-Id: Ie8a660dd139c382929485ff458b5945e8ad72d23
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213957
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This needs to be executed in both romstage and ramstage
for the different PEI binary stages.
It uses the broadwell interface now instead of haswell.
Auron clone of Samus commit 89f98a27ea.
BUG=chrome-os-partner:31286
TEST=Compile only.
BRANCH=None.
Change-Id: I57f4d6f17c589e1b42ee20e6824c77eb382b44af
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213956
