auron: Move SPD related files/information to spd directory
Auron port of Samus commit f40e447cee
BUG=chrome-os-partner:31286
TEST=compile ok and make sure the spd index is right on auron
boot to OS
BRANCH=None
Change-Id: Idf8f58dc48ff7dd2481177aa377628cfa032b699
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/214820
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
This commit is contained in:
Kane Chen
chrome-internal-fetch
parent
d7da2dcce9
commit
0da45307be
10 changed files with 224 additions and 107 deletions
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@ -17,6 +17,8 @@
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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subdirs-y += spd
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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@ -26,31 +28,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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romstage-y += pei_data.c
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ramstage-y += pei_data.c
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## DIMM SPD for on-board memory
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romstage-y += spd.c
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SPD_BIN = $(obj)/spd.bin
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# Order of names in SPD_SOURCES is important!
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SPD_SOURCES = Micron_4KTF25664HZ # 0: 4GB / CH0 + CH1
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SPD_SOURCES += Hynix_HMT425S6AFR6A # 1: 4GB / CH0 + CH1
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SPD_SOURCES += Elpida_EDJ4216EFBG # 2: 4GB / CH0 + CH1
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SPD_SOURCES += Micron_4KTF25664HZ # 3: Reserved / place holder
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SPD_SOURCES += Micron_4KTF25664HZ # 4: 2GB / CH0 + CH1
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SPD_SOURCES += Hynix_HMT425S6AFR6A # 5: 2GB / CH0 + CH1
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SPD_SOURCES += Elpida_EDJ4216EFBG # 6: 2GB / CH0 + CH1
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
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# Include spd rom data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do echo -e -n "\\x$$c"; \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := 0xab
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spd.bin-position := 0xfffec000
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@ -26,7 +26,7 @@
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#include <broadwell/pei_data.h>
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#include <broadwell/pei_wrapper.h>
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#include <broadwell/romstage.h>
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#include "spd.h"
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#include <mainboard/google/auron/spd/spd.h>
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#include "gpio.h"
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void mainboard_romstage_entry(struct romstage_params *rp)
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@ -1,78 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/byteorder.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <string.h>
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#include <broadwell/gpio.h>
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#include <broadwell/pei_data.h>
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#include <broadwell/romstage.h>
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#include "gpio.h"
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#include "spd.h"
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *pei_data)
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{
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int spd_gpio[3];
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int spd_index;
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int spd_file_len;
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struct cbfs_file *spd_file;
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spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
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spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
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spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
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spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
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printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
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spd_index,
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SPD_GPIO_BIT2, spd_gpio[2],
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SPD_GPIO_BIT1, spd_gpio[1],
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SPD_GPIO_BIT0, spd_gpio[0]);
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spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
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if (!spd_file)
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die("SPD data not found.");
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spd_file_len = ntohl(spd_file->len);
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if (spd_index > 3)
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pei_data->dimm_channel1_disabled = 3;
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if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
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printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
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spd_index = 0;
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}
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if (spd_file_len < SPD_LEN)
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die("Missing SPD data.");
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spd_index *= SPD_LEN;
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memcpy(pei_data->spd_data[0][0],
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((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
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/* Index 0-2 are 4GB config with both CH0 and CH1.
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* Index 4-6 are 2GB config with CH0 only. */
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if (spd_index > 3)
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pei_data->dimm_channel1_disabled = 3;
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else
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memcpy(pei_data->spd_data[1][0],
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((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
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}
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54
src/mainboard/google/auron/spd/Makefile.inc
Normal file
54
src/mainboard/google/auron/spd/Makefile.inc
Normal file
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@ -0,0 +1,54 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2014 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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romstage-y += spd.c
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SPD_BIN = $(obj)/spd.bin
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# { GPIO47, GPIO9, GPIO13 }
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SPD_SOURCES = Micron_4KTF25664HZ # 0b0000
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SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0001
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SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0010
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SPD_SOURCES += Micron_4KTF25664HZ # 0b0011
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SPD_SOURCES += Micron_4KTF25664HZ # 0b0100
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SPD_SOURCES += Hynix_HMT425S6AFR6A # 0b0101
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SPD_SOURCES += Elpida_EDJ4216EFBG # 0b0110
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SPD_SOURCES += empty # 0b0111
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SPD_SOURCES += empty # 0b1000
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SPD_SOURCES += empty # 0b1001
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SPD_SOURCES += empty # 0b1010
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SPD_SOURCES += empty # 0b1011
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SPD_SOURCES += empty # 0b1100
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SPD_SOURCES += empty # 0b1101
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SPD_SOURCES += empty # 0b1110
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SPD_SOURCES += empty # 0b1111
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd rom data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do echo -e -n "\\x$$c"; \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := 0xab
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16
src/mainboard/google/auron/spd/empty.spd.hex
Normal file
16
src/mainboard/google/auron/spd/empty.spd.hex
Normal file
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@ -0,0 +1,16 @@
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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141
src/mainboard/google/auron/spd/spd.c
Normal file
141
src/mainboard/google/auron/spd/spd.c
Normal file
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@ -0,0 +1,141 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/byteorder.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <string.h>
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#include <broadwell/gpio.h>
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#include <broadwell/pei_data.h>
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#include <broadwell/romstage.h>
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#include <ec/google/chromeec/ec.h>
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#include <mainboard/google/auron/ec.h>
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#include <mainboard/google/auron/gpio.h>
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#include <mainboard/google/auron/spd/spd.h>
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
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const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
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const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
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const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
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const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
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const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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char spd_name[SPD_PART_LEN+1] = { 0 };
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int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
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int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
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int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
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int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
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int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
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int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
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int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
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/* Module type */
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printk(BIOS_INFO, "SPD: module type is ");
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switch (spd[SPD_DRAM_TYPE]) {
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case SPD_DRAM_DDR3:
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printk(BIOS_INFO, "DDR3\n");
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break;
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case SPD_DRAM_LPDDR3:
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printk(BIOS_INFO, "LPDDR3\n");
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break;
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default:
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printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
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break;
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}
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/* Module Part Number */
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memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
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spd_name[SPD_PART_LEN] = 0;
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printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
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printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
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, banks, ranks, rows, cols);
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printk(BIOS_INFO, "density %d Mb\n", capmb);
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printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
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devw, busw);
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if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
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/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
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printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
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capmb / 8 * busw / devw * ranks);
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}
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}
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/* Copy SPD data for on-board memory */
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void mainboard_fill_spd_data(struct pei_data *pei_data)
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{
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int spd_bits[3] = {
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SPD_GPIO_BIT0,
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SPD_GPIO_BIT1,
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SPD_GPIO_BIT2
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};
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int spd_gpio[3];
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int spd_index;
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int spd_file_len;
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struct cbfs_file *spd_file;
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spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
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spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
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spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
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spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
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printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
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spd_index,
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spd_bits[2], spd_gpio[2],
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spd_bits[1], spd_gpio[1],
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spd_bits[0], spd_gpio[0]);
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spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
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if (!spd_file)
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die("SPD data not found.");
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spd_file_len = ntohl(spd_file->len);
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if (spd_index > 3)
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pei_data->dimm_channel1_disabled = 3;
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if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
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printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
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spd_index = 0;
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}
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if (spd_file_len < SPD_LEN)
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die("Missing SPD data.");
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spd_index *= SPD_LEN;
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memcpy(pei_data->spd_data[0][0],
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((char *)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
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/* Index 0-2 are 4GB config with both CH0 and CH1.
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* Index 4-6 are 2GB config with CH0 only. */
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if (spd_index > 3)
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pei_data->dimm_channel1_disabled = 3;
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else
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memcpy(pei_data->spd_data[1][0],
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((char *)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
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/* Make sure a valid SPD was found */
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if (pei_data->spd_data[0][0][0] == 0)
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die("Invalid SPD data.");
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mainboard_print_spd_info(pei_data->spd_data[0][0]);
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}
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@ -22,6 +22,16 @@
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#define SPD_LEN 256
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0b
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#define SPD_DRAM_LPDDR3 0xf1
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_ORGANIZATION 7
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#define SPD_BUS_DEV_WIDTH 8
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#define SPD_PART_OFF 128
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#define SPD_PART_LEN 18
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/* Auron board memory configuration GPIOs */
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#define SPD_GPIO_BIT0 13
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#define SPD_GPIO_BIT1 9
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